PHD_PHP36N03LT_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 8 June 2006 2 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
3. Ordering information
4. Limiting values
Table 2. Ordering information
Type number Package
Name Description Version
PHD36N03LT DPAK plastic single-ended surface-mounted package; 3 leads (one lead
cropped)
SOT428
PHP36N03LT SC-46 plastic single-ended package; heatsink mounted; 1 mounting hole;
3-lead TO-220AB
SOT78
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
drain-source voltage 25 °C ≤ T
j
≤ 175 °C - 30 V
V
DGR
drain-gate voltage (DC) 25 °C ≤ T
j
≤ 175 °C; R
GS
=20kΩ -30V
V
GS
gate-source voltage - ±20 V
I
D
drain current T
mb
=25°C; V
GS
= 10 V; see Figure 2 and 3 - 43.4 A
T
mb
= 100 °C; V
GS
= 10 V; see Figure 2 - 30.7 A
I
DM
peak drain current T
mb
=25°C; pulsed; t
p
≤ 10 µs; see Figure 3 - 173.6 A
P
tot
total power dissipation T
mb
=25°C; see Figure 1 - 57.6 W
T
stg
storage temperature −55 +175 °C
T
j
junction temperature −55 +175 °C
Source-drain diode
I
S
source current T
mb
=25°C - 43.4 A
I
SM
peak source current T
mb
=25°C; pulsed; t
p
≤ 10 µs - 173.6 A
