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ADM1060ARUZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
ADM1060
Rev. B | Page 27 of 52
Hex
Address Table Name
Default Power-
On Value Description
84 Table 33 P9GPIPOL 0x00
Polarity sense and ignore mask bits for all four GPIs when used as inputs
to the A function of PLB9
85 Table 34 P9GPIIMK 0x00
Polarity sense and ignore mask bits for all four GPIs when used as inputs
to the B function of PLB9
86 Table 35 P9WDICFG 0x00
Polarity sense and ignore mask bits for the pulsed and latched outputs of
the watchdog detector when used as inputs to both A and B functions of
PLB9
87 Table 36 PS9EN 0x00 Enable bits for A and B functions of PLB9, polarity bit for PLB9 output
88 Table 29 P9PLBPOLB 0x00
Polarity sense for all eight other PLB outputs when used as inputs to the
B function of PLB9
89 Table 30 P9PLBIMKB 0x00
Ignore mask for all eight other PLB outputs when used as inputs to the B
function of PLB9
8A Table 31 P9SFDPOLB 0x00
Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B
function of PLB9
8B Table 32 P9SFDIMKB 0x00
Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the B
function of PLB9
ADM1060
Rev. B | Page 28 of 52
PLBA REGISTER BIT MAPS
Table 29. PnPLBPOLA/PnPLBPOLB Registers Bit Map (Power-On Default 0x00)
Bit Name R/W Description
7–0 POL9−POL1 R/W
If high, invert the PLBn input before it is used in function A or B.
PLB1 PLB2 PLB3 PLB4 PLB5 PLB6 PLB7 PLB8 PLB9
Function A 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
Function B 0x08 0x18 0x28 0x38 0x48 0x58 0x68 0x78 0x88
7 PLB9 PLB9 PLB9 PLB9 PLB9 PLB9 PLB9 PLB9 PLB8
6 PLB8 PLB8 PLB8 PLB8 PLB8 PLB8 PLB8 PLB7 PLB7
5 PLB7 PLB7 PLB7 PLB7 PLB7 PLB7 PLB6 PLB6 PLB6
4 PLB6 PLB6 PLB6 PLB6 PLB6 PLB5 PLB5 PLB5 PLB5
3 PLB5 PLB5 PLB5 PLB5 PLB4 PLB4 PLB4 PLB4 PLB4
2 PLB4 PLB4 PLB4 PLB3 PLB3 PLB3 PLB3 PLB3 PLB3
1 PLB3 PLB3 PLB2 PLB2 PLB2 PLB2 PLB2 PLB2 PLB2
0 PLB2 PLB1 PLB1 PLB1 PLB1 PLB1 PLB1 PLB1 PLB1
Table 30. PnPLBIMKA/PnPLBIMKB Registers Bit Map (Power-On Default 0x00)
Bit Name R/W Description
7–0 IGN9–IGN1 R/W
If high, mask the PLBn input before it is used in function A or B.
PLB1 PLB2 PLB3 PLB4 PLB5 PLB6 PLB7 PLB8 PLB9
Function A 0x01 0x11 0x21 0x31 0x41 0x51 0x61 0x71 0x81
Function B 0x09 0x19 0x29 0x39 0x49 0x59 0x69 0x79 0x89
7 PLB9 PLB9 PLB9 PLB9 PLB9 PLB9 PLB9 PLB9 PLB8
6 PLB8 PLB8 PLB8 PLB8 PLB8 PLB8 PLB8 PLB7 PLB7
5 PLB7 PLB7 PLB7 PLB7 PLB7 PLB7 PLB6 PLB6 PLB6
4 PLB6 PLB6 PLB6 PLB6 PLB6 PLB5 PLB5 PLB5 PLB5
3 PLB5 PLB5 PLB5 PLB5 PLB4 PLB4 PLB4 PLB4 PLB4
2 PLB4 PLB4 PLB4 PLB3 PLB3 PLB3 PLB3 PLB3 PLB3
1 PLB3 PLB3 PLB2 PLB2 PLB2 PLB2 PLB2 PLB2 PLB2
0 PLB2 PLB1 PLB1 PLB1 PLB1 PLB1 PLB1 PLB1 PLB1
Table 31. PnSFDPOLA/PnSFDPOLB Registers Bit Map (Power-On Default 0x00)
Bit Name R/W Description
7 Reserved N/A Cannot Be Used
6–0 POL7−POL1 R/W
If high, invert the SFDn input before it is used in function A or B.
PLB1 PLB2 PLB3 PLB4 PLB5 PLB6 PLB7 PLB8 PLB9
Function A 0x02 0x12 0x22 0x32 0x42 0x52 0x62 0x72 0x82
Function B 0x0A 0x1A 0x2A 0x3A 0x4A 0x5A 0x6A 0x7A 0x8A
6 VP4 VP4 VP4 VP4 VP4 VP4 VP4 VP4 VP4
5 VP3 VP3 VP3 VP3 VP3 VP3 VP3 VP3 VP3
4 VP2 VP2 VP2 VP2 VP2 VP2 VP2 VP2 VP2
3 VP1 VP1 VP1 VP1 VP1 VP1 VP1 VP1 VP1
2 VH VH VH VH VH VH VH VH VH
1 VB2 VB2 VB2 VB2 VB2 VB2 VB2 VB2 VB2
0 VB1 VB1 VB1 VB1 VB1 VB1 VB1 VB1 VB1
ADM1060
Rev. B | Page 29 of 52
Table 32. PnSFDIMKA/PnSFDIMKB Registers Bit Map (Power-On Default 0x00)
Bit Name R/W Description
7 Reserved N/A Cannot Be Used
6−0 IGN7−IGN1 R/W
If high, mask the SFDn input before it is used in function A or B.
PLB1 PLB2 PLB3 PLB4 PLB5 PLB6 PLB7 PLB8 PLB9
Function A
0x03 0x13 0x23 0x33 0x43 0x53 0x63 0x73 0x83
Function B
0x0B 0x1B 0x2B 0x3B 0x4B 0x5B 0x6B 0x7B 0x8B
6 VP4 VP4 VP4 VP4 VP4 VP4 VP4 VP4 VP4
5 VP3 VP3 VP3 VP3 VP3 VP3 VP3 VP3 VP3
4 VP2 VP2 VP2 VP2 VP2 VP2 VP2 VP2 VP2
3 VP1 VP1 VP1 VP1 VP1 VP1 VP1 VP1 VP1
2 VH VH VH VH VH VH VH VH VH
1 VB2 VB2 VB2 VB2 VB2 VB2 VB2 VB2 VB2
0 VB1 VB1 VB1 VB1 VB1 VB1 VB1 VB1 VB1
Table 33. PnGPIPOL Registers Bit Map (Power-On Default 0x00)
Bit Name R/W Description
7−4 APOL4−APOL1 R/W
If high, invert the GPIn input before it is used in function A.
3−0 BPOL4−BPOL1 R/W
If high, invert the GPIn input before it is used in function B.
PLB1 PLB2 PLB3 PLB4 PLB5 PLB6 PLB7 PLB8 PLB9
0x04 0x14 0x24 0x34 0x44 0x54 0x64 0x74 0x84
7 GPI1 GPI1 GPI1 GPI1 GPI1 GPI1 GPI1 GPI1 GPI1
6 GPI2 GPI2 GPI2 GPI2 GPI2 GPI2 GPI2 GPI2 GPI2
5 GPI3 GPI3 GPI3 GPI3 GPI3 GPI3 GPI3 GPI3 GPI3
4
Function A
GPI4 GPI4 GPI4 GPI4 GPI4 GPI4 GPI4 GPI4 GPI4
3 GPI1 GPI1 GPI1 GPI1 GPI1 GPI1 GPI1 GPI1 GPI1
2 GPI2 GPI2 GPI2 GPI2 GPI2 GPI2 GPI2 GPI2 GPI2
1 GPI3 GPI3 GPI3 GPI3 GPI3 GPI3 GPI3 GPI3 GPI3
0
Function B
GPI4 GPI4 GPI4 GPI4 GPI4 GPI4 GPI4 GPI4 GPI4
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

ADM1060ARUZ-REEL7

Mfr. #:
Buy ADM1060ARUZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits Communications SupvSeq Circuit I.C.
Lifecycle:
New from this manufacturer.
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