ADM1060
Rev. B | Page 6 of 52
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUTS (GPI 1–4, WDI, A0, A1)
4
Input High Voltage, V
IH
2.0 V
Input Low Voltage, V
IL
0.8 V
Input High Current, I
IH
–1 µA V
IN
= 5.5 V
Input Low Current, I
IL
1 µA V
IN
= 0 V
Input Capacitance 10 pF
Programmable Pull-Down Current, I
PULLDOWN
10 µA If known logic state required
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, V
IH
2.0 V
Input Low Voltage, V
IL
0.8 V
Output Low Voltage, V
OL
0.4 V I
OUT
= −3.0 mA
PROGRAMMABLE DELAY BLOCK
Timeout 0 500 ms
16 programmable options on both rising and
falling edge
WATCHDOG TIMER INPUT
Timeout 0 12.8 s Eight programmable timeout options
EEPROM RELIABILITY
Endurance
5, 6
Data Retention
7
100
10
Kcycles
Years
SERIAL BUS TIMING
8
Clock Frequency, f
SCLK
400 kHz See Figure 27
Glitch Immunity, t
SW
50 ns See Figure 27
Bus Free Time, t
BUF
4.7 µs See Figure 27
Start Setup Time, t
SU;STA
4.7 µs See Figure 27
Start Hold Time, t
HD;STA
4 µs See Figure 27
SCL Low Time, t
LOW
4.7 µs See Figure 27
SCL High Time, t
HIGH
4 µs See Figure 27
SCL, SDA Rise Time, t
r
1000 ns See Figure 27
SCL, SDA Fall Time, t
f
300 µs See Figure 27
Data Setup Time, t
SU;DAT
250 ns See Figure 27
Data Hold Time, t
HD;DAT
300 ns See Figure 27
NOTES
1
At least one VPn must be ≥3.0 V if used as supply. VH must be ≥4.5 V if used as supply.
2
Specification is not production tested, but is supported by characterization data at initial product release.
3
1% threshold accuracy is only achievable on parts preprogrammed by Analog Devices. Contact ADM1060.program@analog.com for further details.
4
Logic inputs will accept input high voltages up to 5.5 V even when the device is operating at supply voltages below 5 V.
5
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40°C, +25°C, and +85°C.
6
For programming and erasing of EEPROM, a minimum V
DD
= 3.0 V is required 0°C to +85°C and a minimum V
DD
= 4.5 V is required −40°C to 0°C.
7
Retention lifetime equivalent at junction temperature (T
J
) = 55°C as per JEDEC Std. 22 method A117.
8
Timing specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.0 V for a rising edge.
