ADM1060
Rev. B | Page 45 of 52
2. To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case, the
command byte is the high byte of the EEPROM address from
0xF8 to 0xF9. The (only) data byte is the low byte of the
EEPROM address. This is illustrated in Figure 31.
S
A
12 345678
SLAVE
ADDRESS
EEPROM
ADDRESS
HIGH BYTE
(0xF8 TO 0xF9)
EEPROM
ADDRESS
LOW BYTE
(0x00 TO 0xFF)
WA
A
P
Figure 31. Setting an EEPROM Address
Note for page erasure that as a page consists of 32 bytes, only
the three MSBs of the address low byte are important. The
lower five bits of the EEPROM address low byte only specify
addresses within a page and are ignored during an erase
operation.
3. To write a single byte of data to EEPROM. In this case the
command byte is the high byte of the EEPROM address from
0xF8 to 0xF9. The first data byte is the low byte of the
EEPROM address and the second data byte is the actual data.
This is illustrated in Figure 32.
SAP
12 345678910
SLAVE
ADDRESS
DATA
EEPROM
ADDRESS
HIGH BYTE
(0xF8 TO0xF9)
EEPROM
ADDRESS
LOW BYTE
(0x00 TO0xFF)
W
A
AA
Figure 32. Single Byte Write to EEPROM
BLOCK WRITE
In this operation, the master device writes a block of data to a
slave device. The start address for a block write must previously
have been set. In the case of the ADM1060, this is done by a
Send Byte operation to set a RAM address or a Write Byte/Word
operation to set an EEPROM address.
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the write
bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code that tells the slave device
to expect a block write. The ADM1060 command code for a
block write is 0xFC (1111 1100 binary).
5. The slave asserts ACK on SDA.
6. The master sends a data byte that tells the slave device how
many data bytes will be sent. The SMBus specification allows
a maximum of 32 data bytes to be sent in a block write.
7. The slave asserts ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts ACK on SDA after each data byte.
10. The master asserts a STOP condition on SDA to end the
transaction.
SWA A AA PA A
12 3 4 56789 10
SLAVE
ADDRESS
COMMAND 0xFC
(BLOCK WRITE)
BYTE
COUNT
DATA 1 DATA 2
DATA N
Figure 33. Block Write to EEPROM or RAM
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except
1. There must be at least N locations from the start address to
the highest EEPROM address (0xF9FF) to avoiding writing
to invalid addresses.
2. If the addresses cross a page boundary, both pages must be
erased before programming.
Note that the ADM1060 features a clock extend function for
writes to EEPROM. Programming an EEPROM byte takes
approximately 250 µs, which would limit the SMBus clock for
repeated or block write operations. The ADM1060 pulls SCL
low and extends the clock pulse when it cannot accept any more
data.
READ OPERATIONS
The ADM1060 uses the following SMBus read protocols:
RECEIVE BYTE
In this operation, the master device receives a single byte from a
slave device, as follows:
1. The master device asserts a START condition on SDA.
2. The master sends the 7-bit slave address followed by the read
bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a STOP condition on SDA and the trans-
action ends.
In the ADM1060, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation. This is illustrated in Figure 34.
SRA
P
12 3456
SLAVE
ADDRESS
DATA A
Figure 34. Single Byte Read from EEPROM or RAM
ADM1060
Rev. B | Page 46 of 52
BLOCK READ
In this operation, the master device reads a block of data from a
slave device. The start address for a block read must previously
have been set. In the case of the ADM1060, this is done by a
Send Byte operation to set a RAM address, or a Write
Byte/Word operation to set an EEPROM address. The block
read operation itself consists of a Send Byte operation that
sends a block read command to the slave, immediately followed
by a repeated start and a read operation that reads out multiple
data bytes, as follows:
1. The master device asserts a START condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code that tells the slave device
to expect a block read. The ADM1060 command code for a
block read is 0xFD (1111 1101 binary).
5. The slave asserts ACK on SDA.
6. The master asserts a repeat start condition on SDA.
7. The master sends the 7-bit slave address followed by the
read bit (high).
8. The slave asserts ACK on SDA.
9. The ADM1060 sends a byte count data byte that tells the
master how many data bytes to expect. The ADM1060 will
always return 32 data bytes (0x20), which is the maximum
allowed by the SMBus 1.1 specification.
10. The master asserts ACK on SDA.
11. The master receives 32 data bytes.
12. The master asserts ACK on SDA after each data byte.
13. The master asserts a STOP condition on SDA to end the
transaction.
SWA
A
A
AA S RA
12 3 4 567 89101112
13
14
P
SLAVE
ADDRESS
COMMAND 0xFD
(BLOCK READ)
SLAVE
ADDRESS
BYTE
COUNT
DATA 1
DATA
32
Figure 35. Block Read from EEPROM or RAM
ERROR CORRECTION
The ADM1060 provides the option of issuing a PEC (packet
error correction) byte after a write to RAM, a write to
EEPROM, a block write to RAM/EEPROM, or a block read
from RAM/EEPROM. This enables the user to verify that the
data received by or sent from the ADM1060 is correct. The PEC
byte is an optional byte sent after the last data byte has been
written to or read from the ADM1060. The protocol is as
follows:
1. The ADM1060 issues a PEC byte to the master. The master
should check the PEC byte and issue another block read if the
PEC byte is incorrect.
2. A NACK is generated after the PEC byte to signal the end of
the read.
Note: The PEC byte is calculated using CRC-8. The Frame
Check Sequence (FCS) conforms to CRC-8 by the polynomial
C(x) = x
8
+ x
2
+ x
1
+ 1
Consult the SMBus 1.1 specification for more information. An
example of a block read with the optional PEC byte is shown in
Figure 36.
SWA
A
AA S RA
12 3 4 567 89101112
SLAVE
ADDRESS
COMMAND 0xFD
(BLOCK READ)
SLAVE
ADDRESS
BYTE
COUNT
DATA 1
A
13
P
15
A
14
PEC
DATA
32
Figure 36. Block Read from EEPROM or RAM with PEC
ADM1060
Rev. B | Page 47 of 52
8
9
10
11
12
13
14
28
27
26
25
24
VH
VP1
VP2
VP3
VP4
VB1
VB2
GPI1
GPI2
GPI3
GPI4
WDI
4
321
SCL
A1
SDA
A0
15
16
18
19
20
21
22
23
PDO9
PDO8
PDO7
PDO6
PDO5
PDO4
PDO2
PDO1
17
PDO3
5
VDDCAP
VCCP
7
ADM1060
ACK
CLKOUT
VIN_I/O
PWRGOOD
RESET
µP
VIN
EN
VOUT
VIN
EN
VOUT
VIN
PWRGD
LDO
0.9V_OUT
12V_IN
3.3VSB_IN
3.3V_IN
5VSB_IN
5V_IN
3.3VSB_OUT
3.3V_OUT
5VSB_OUT
5V_OUT
–5V_OUT
PWR_OK
3.3V
VIN_CORE
VOUT
1.8V
1
µ
F
1
µ
F
INVERTER
DC/DC
CONVERTER
Figure 37. ADM1060 Application Diagram

ADM1060ARUZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits Communications SupvSeq Circuit I.C.
Lifecycle:
New from this manufacturer.
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