ADM1060
Rev. B | Page 3 of 52
GENERAL DESCRIPTION
(continued from Page 1)
All of the inputs and outputs described previously are
controlled by the programmable logic block array (PLBA). This
is the logic core of the ADM1060. It is comprised of nine
macrocells, one for each PDO. These macrocells are essentially
just wide AND gates. Any/all of the inputs can be used as an
input to these macrocells. The output of a macrocell can also be
used as an input to any macrocell other than itself (an input to
itself would result in a nonterminating loop). The PLBA outputs
control the PDOs of the ADM1060 via delay blocks, where a
delay of 0 ms to 500 ms can be programmed on the rising
and/or the falling edge of the data. This results in a very flexible
sequencing ability. Thus, for instance, PDO1 can be
programmed so that it will not assert until the VP2, VP3, and
VP4 supplies are in tolerance; VB1 and VH have been in
tolerance for 200 ms; and PDO7 has already been asserted. A
simple sequencing operation would be to daisy-chain each PLB
output into the input of the next PLB such that PDO9 does not
assert until PDO8 asserts, which in turn does not assert until
PDO7 asserts, and so on.
All of the functional capability described here is programmable
through the industry-standard 2-wire bus (SMBus) provided.
Device settings can be written to EEPROM memory for auto-
matic programming of the device on power-up. The EEPROM
is organized in 512 bytes, half of which are used to program all
of the functions on the ADM1060. The other 256 bytes of
EEPROM are for general-purpose system use such as date codes
and system ID. Read/write access to this is also via the 2-wire
interface. In addition, each output state can be directly over-
driven from the serial interface, allowing a further level of
control, as in a system controlled soft power-down.
ADM1060
Rev. B | Page 4 of 52
8
9
10
11
12
13
14
28
27
26
25
24
6
7
5
43
21
15
16
17
18
19
20
21
22
23
VH
VP1
VP2
VP3
VP4
VB1
VB2
GPI1
GPI2
GPI3
GPI4
WDI
GND
V
CCP
VDDCAP
SCL
SDA
A1
SDA
A0
PDO9
PDO8
PDO7
PDO6
PDO5
PDO4
PDO3
PDO2
PDO1
PDO9
PDO8
PDO7
PDO6
PDO5
PDO4
PDO3
PDO2
PDO1
PROGRAMMABLE
DELAY BLOCKS
PDB9
PDB8
PDB7
PDB6
PDB5
PDB4
PDB3
PDB2
PDB1
PLB
MACROCELL 1
PLB
MACROCELL 2
PLB
MACROCELL 3
PLB
MACROCELL 4
PLB
MACROCELL 5
PLB
MACROCELL 6
PLB
MACROCELL 7
PLB
MACROCELL 8
PLB
MACROCELL 9
PROGRAMMABLE
LOGIC BLOCK
ARRAY
(PLBA)
HIGH SUPPLY
(14.4V)
FAULT DETECTOR
POSITIVE
SUPPLY FAULT
DETECTOR 1
POSITIVE
SUPPLY FAULT
DETECTOR 4
BIPOLAR
SUPPLY FAULT
DETECTOR 1
BIPOLAR
SUPPLY FAULT
DETECTOR 2
INPUT LOGIC
SIGNAL
CONDITION
WATCHDOG
FAULT
DETECTOR
VREF
ADM1060
INTERNAL
5.25V SUPPLY
REGULATED
5.25V SUPPLY
CHARGE PUMP
V
DD
ARBITRATOR
SMBus INTERFACE
DEVICE
CONTROLLER
EEPROM
DATA, ADDRESS, AND
WRITE ENABLE BUSES
TO STORE CONTROL
INFORMATION LOCAL
TO FUNCTIONS
t
RISE
t
FALL
t
RISE
t
FALL
t
RISE
t
FALL
t
RISE
t
FALL
t
RISE
t
FALL
t
RISE
t
FALL
t
RISE
t
FALL
t
RISE
t
FALL
t
RISE
t
FALL
SMBus DATA
100kHz CLOCK
Figure 1. Functional Block Diagram
ADM1060
Rev. B | Page 5 of 52
SPECIFICATIONS
(VH = 4.75 V to 14.4 V, VPn = 3.0 V to 6.0 V,
1
T
A
= −40°C to +85°C, unless otherwise noted.)
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY ARBITRATION
VDDCAP 2.7 V Any VPn ≥ 3.0 V
2.7 V VH ≥ 4.75 V
4.75 5.1 V Any VPn = 6.0 V
4.75 5.1 V VH = 14.4 V
POWER SUPPLY
Supply Current, I
DD
3 mA
VDDCAP = 4.75 V, no PDO FET drivers on, no
loaded PDO pull-ups to VDDCAP
5 mA
VDDCAP = 4.75 V, all PDO FET drivers on (loaded
with 1 µA), no PDO pull-ups to VDDCAP
Additional Current Available
from VDDCAP
2
1 mA
Max additional load that can be drawn from PDO
pull-ups to VDDCAP
SUPPLY FAULT DETECTORS
Input Impedance
VH Input 52 kΩ From VH to GND
VPn Inputs 52 kΩ From VPn to GND
VBn Inputs 190 kΩ From VBn to 2.25 V (internal reference)
52 kΩ From VBn to GND (positive mode)
30 kΩ From VBn to GND (negative mode)
Absolute Accuracy (VH, VPn, VBn Inputs) –2.5 +2.5 %
Calibrated Absolute Accuracy
3
VH, VPn Inputs –1.0 +1.0 %
Factory preprogrammed to specific thresholds
VBn Inputs –1.5 +1.5 % Factory preprogrammed to specific thresholds
Glitch Filters (Digital) 0 100 µs
See Figure 19. Eight timeout options between 0 µs
and 100 µs
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode
(PDOs 1 to 4)
Output Impedance, R
OUT
440 kΩ
V
OH
11 12.5 14 V I
OH
= 0 µA
10.5 12 V I
OH
= 1 µA
I
OUTAVG
20 µA 2 V < V
OH
< 7 V
Standard (Digital Output) Mode
(PDOs 1 to 9)
V
OH
2.4 V V
PU
(pull-up to VDDCAP or VPn) > 2.7 V, I
OH
= 1 mA
4.5 V V
PU
to VPn = 6.0 V, I
OH
= 0 mA
VPU – 0.3 V V
PU
≤ 2.7 V, I
OH
= 1 mA
V
OL
0.4 V I
OL
= 2 mA
1.2 V I
OL
= 10 mA
2.0 V I
OL
= 15 mA
I
SINK
2
20 mA Total sink current (PDO1–PDO9)
R
PULLUP-
Weak Pull-Up 20 kΩ Internal pull-up
I
SOURCE (VPn)
2
2 mA
Current load on any VPn pull-up (i.e., total source
current available through any number of PDO
pull-up switches configured on to any one)
Three-State Output Leakage Current 10 µA V
PDO
= 14.4 V

ADM1060ARUZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits Communications SupvSeq Circuit I.C.
Lifecycle:
New from this manufacturer.
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