MT16HTF25664AY-667EA3 Datasheet MT16HTF12864AY-40EB1, MT16HTF12864AY-40EB3, MT16HTF12864AY-40ED1 | P4-P6

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN

512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM

Pin Assignments and Descriptions

Table 5: Pin Descriptions

Pin numbers may not correlate with symbols; refer to Table 4 on page 3 for more information

Pin Numbers Symbol Type Description

77, 195 ODT0, ODT1 Input

On-die termination: ODT (registered HIGH) enables termination

resistance internal to the DDR2 SDRAM. When enabled, ODT is

only applied to each of the following pins: DQ, DQS, DQS#, and

DM. The ODT input will be ignored if disabled via the LOAD

MODE command.

137, 138, 185, 186, 220, 221 CK0, CK0#,

CK1, CK1#,

CK2, CK2#

Input

Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive

edge of CK and negative edge of CK#. Output data (DQs and

DQS/DQS#) is referenced to the crossings of CK and CK#.

52, 171 CKE0, CKE1 Input

Clock enable: CKE (registered HIGH) activates and CKE

(registered LOW) deactivates clocking circuitry on the DDR2

SDRAM. The specific circuitry that is enabled/disabled is

dependent on the DDR2 SDRAM configuration and operating

mode. CKE LOW provides precharge power-down and SELF

REFRESH operations (all device banks idle), or ACTIVE power-

down (row ACTIVE in any device bank). CKE is synchronous for

power-down entry, power-down exit, output disable, and for

SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit.

Input buffers (excluding CK, CK#, CKE, and ODT) are disabled

during power-down. Input buffers (excluding CKE) are disabled

during SELF REFRESH. CKE is an SSTL_18 input but will detect a

LVCMOS LOW level when V

DD is applied during first power-up.

After VREF has become stable during the power on and

initialization sequence, it must be maintained for proper

operation of the CKE receiver. For proper SELF REFRESH

operation, V

REF must be maintained to this input.

76, 193 S0#, S1# Input

Chip select: S# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when

S# is registered HIGH. S# provides for external rank selection on

systems with multiple ranks. S# is considered part of the

command code.

73, 74, 192 RAS#, CAS#, WE# Input

Command inputs: RAS#, CAS#, and WE# (along with S#) define

the command being entered.

54 (2GB), 71, 190 BA0, BA1,

BA2 (2GB)

Input

Bank address inputs: BA0–BA1/BA2 define to which device bank

an ACTIVE, READ, WRITE, or PRECHARGE command is being

applied. BA0–BA1/BA2 define which mode register including

MR, EMR, EMR(2), and EMR(3) is loaded during the LMR

command.

57, 58, 60, 61, 63, 70, 176,

177, 179, 180, 182, 183, 188,

196 (1GB, 2GB)

A0–A12 (512MB)

A0–A13 (1GB, 2GB)

Input

Address inputs: Provide the row address for ACTIVE commands,

and the column address and auto precharge bit (A10) for READ/

WRITE commands, to select one location out of the memory

array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the precharge applies to one

device bank (A10 LOW, device bank selected by BA0–BA1/BA2)

or all device banks (A10 HIGH). The address inputs also provide

the op-code during a LMR command.

125, 134, 146, 155, 202, 211,

223, 232

DM0–DM7 Input

Input data mask: DM is an input mask signal for write data.

Input data is masked when DM is sampled HIGH along with that

input data during a WRITE access. DM is sampled on both edges

of DQS. Although DM pins are input-only, the DM loading is

designed to match that of DQ and DQS pins.

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN

512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM

Pin Assignments and Descriptions

120 SCL Input

Serial clock for presence-detect: SCL is used to synchronize the

presence-detect data transfer to and from the module.

101, 239, 240 SA0–SA2 Input

Presence-detect address inputs: These pins are used to configure

the presence-detect device.

3, 4, 9, 10, 12, 13, 21, 22, 24,

25, 30, 31, 33, 34, 39, 40, 80,

81, 86, 87, 89, 90, 95, 96, 98,

99, 107, 108, 110, 111, 116,

117, 122, 123, 128, 129, 131,

132, 140, 141, 143, 144, 149,

150, 152, 153, 158, 159, 199,

200, 205, 206, 208, 209, 214,

215, 217, 218, 226, 227, 229,

230, 235, 236

DQ0–DQ63 I/O

Data Input/output: Bidirectional data bus.

6, 7, 15, 16, 27, 28, 36, 37,

83, 84, 92, 93, 104, 105, 113,

114,

DQS0–DQS7,

DQS0#–DQS7#

I/O

Data strobe: Output with read data, input with write data for

source synchronous operation. Edge-aligned with read data,

center aligned with write data. DQS# is only used when

differential data strobe mode is enabled via the LOAD MODE

command.

119 SDA I/O

Serial presence-detect data: SDA is a bidirectional pin used to

transfer addresses and data into and out of the presence-detect

portion of the module.

53, 59, 64, 67, 69, 172, 178,

184, 187, 189, 197,

DD Supply

Power supply: +1.8V ±0.1V.

51, 56, 62, 72, 75, 78, 170,

175, 181, 191, 194,

DDQ Supply

DQ Power supply: +1.8V ±0.1V.

REF Supply

SSTL_18 reference voltage.

2, 5, 8, 11, 14, 17, 20, 23, 26,

29, 32, 35, 38, 41, 44, 47, 50,

65, 66, 79, 82, 85, 88, 91, 94,

97,100, 103, 106, 109,112,

115, 118, 121, 124, 127, 130,

133, 136, 139, 142, 145, 148,

151, 154, 157, 160, 163, 166,

169, 198, 201, 204, 207, 210,

213, 216, 219, 222, 225, 228,

231, 234, 237

SS Supply

Ground.

238 V

DDSPD Supply

Serial EEPROM positive power supply: +1.7V to +3.6V.

18, 19, 42, 43, 45, 46, 48, 49,

54 (512MB, 1GB), 55, 68, 76,

102, 125, 126, 134, 135, 146,

147, 155, 156, 161, 162, 164,

165, 167, 168, 171, 173, 174,

196 (512MB), 202, 203, 211,

212, 223, 224, 232, 233

NC –

No connect: These pins should be left unconnected.

Table 5: Pin Descriptions

Pin numbers may not correlate with symbols; refer to Table 4 on page 3 for more information

Pin Numbers Symbol Type Description

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN

512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM

Functional Block Diagram

Unless otherwise noted, resistor values are 22Ω. Micron module part numbers are

explained in the module part numbering guide at www.micron.com/numbering.html.

Modules use the following DDR2 SDRAM devices: MT47H32M8BT (512MB);

MT47H64M8BT (1GB); and MT47H128M8BT (2GB).

Figure 3: Functional Block Diagram

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM CS# DQ DQS#

U19

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

U14

DM CS# DQ DQS#

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM CS# DQ DQS#

U18

DM CS# DQ DQS#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM CS# DQ DQS#

U17

DM CS# DQ DQS#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM CS# DQ DQS#

U16

DM CS# DQ DQS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U13

DM CS# DQ DQS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

U12

DM CS# DQ DQS#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

U11

DM CS# DQ DQS#

DQS0#

DQS0

DM0

S0#

S1#

DQS1#

DQS1

DM1

DQS2#

DQS2

DM2

DQS3#

DQS3

DM3

DQS4#

DQS4

DM4

DQS5#

DQS5

DM5

DQS6#

DQS6

DM6

DQS7#

DQS7

DM7

U4, U6

U14, U16

CK0

CK0#

67Ω

U1–U3,

U17–U19

CK1

CK1#

U7–U10,

U11–U13

CK2

CK2#

Serial PD

SA0 SA1

SA2

SDA

SCL

U10

VDDSPD

VDD, VDDL, VDDQ

VREF

VSS

Serial PD

DDR2 SDRAMS

DDR2 SDRAMS, EEPROM

1pF

BA0–BA1 (512MB, 1GB)

BA0–BA2 (2GB)

A0–A12 (512M)

A0–A13 (1GB, 2GB)

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

BA0–BA1: DDR2 SDRAMs

BA0–BA2: DDR2 SDRAMs

A0–A12: DDR2 SDRAMs

A0–A13: DDR2 SDRAMs

RAS#: DDR2 SDRAMs

CAS#: DDR2 SDRAMs

WE#: DDR2 SDRAMs

CKE0: U1–U4, U6–U9

CKE1: U11–U14, U16–U19

ODT0: U1–U4, U6–U9

ODT1: U11–U14, U16–U19

25pF

7.5Ω

67Ω

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

MT16HTF25664AY-667EA3

Mfr. #:

Buy MT16HTF25664AY-667EA3

Manufacturer:

Micron

Description:

MODULE DDR2 SDRAM 2GB 240UDIMM

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MT16HTF25664AY-667EA3

MT16HTF25664AY-667EA3

Products related to this Datasheet