MT16HTF25664AY-667EA3 Datasheet MT16HTF12864AY-40EB1, MT16HTF12864AY-40EB3, MT16HTF12864AY-40ED1 | P7-P9

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN

512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM

General Description

The MT16HTF6464A, MT16HTF12864A, and MT16HTF25664A DDR2 SDRAM modules

are high-speed, CMOS, dynamic random-access 512MB, 1GB, and 2GB memory

modules organized in x64 configuration. DDR2 modules use internally configured 4-

bank (512MB, 1GB) or 8-bank (2GB) DDR2 devices.

DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-

tion. The double data rate architecture is essentially a 4n-prefetch architecture with an

interface designed to transfer two data words per clock cycle at the I/O pins. A single

read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-

wide, one-clock-cycle data transfer at the internal DDR2 device core and four corre-

sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for

use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 device

during READs and by the memory controller during WRITEs. DQS is edge-aligned with

data for READs and center-aligned with data for WRITEs.

DDR2 modules operate from a differential clock (CK and CK#); the crossing of CK going

HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands

(address and control signals) are registered at every positive edge of CK. Input data is

registered on both edges of DQS, and output data is referenced to both edges of DQS, as

well as to both edges of CK.

Serial Presence-Detect Operation

DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is

implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256

bytes. The first 128 bytes can be programmed by Micron to identify the module type and

various DDR2 organizations and timing parameters. The remaining 128 bytes of storage

are available for use by the customer. System READ/WRITE operations between the

master (system logic) and the slave EEPROM device occur via a standard I

C bus using

the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide

eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the

module, permanently disabling hardware write protect.

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN

512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM

Electrical Specifications

Stresses greater than those listed in Table 6 may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

Notes: 1. S# is defined to be S0# and S1#. CKE includes both CKE0 and CKE1.

2. V

DDL is the power supply for the DDR2 devices’ DLL; however, this power supply is not

brought directy to a DIMM pin.

Capacitance

At DDR2 data rates, Micron encourages designers to simulate the performance of the

module to achieve optimum values. When inductance and delay parameters associated

with trace lengths are used in simulations, they are significantly more accurate and real-

istic than a gross estimation of module capacitance. Simulations can then render a

considerably more accurate result. JEDEC modules are now designed by using simula-

tions to close timing budgets.

Table 6: Absolute Maximum Ratings

Parameter Symbol Min Max Units

DD supply voltage relative to VSS

VDD –1.0 2.3 V

DDQ supply voltage relative to VSS

VDDQ–0.52.3 V

DDL supply voltage relative to Vss

VDDL

–0.5 2.3 V

Voltage on any pin relative to V

VIN, VOUT –0.5 2.3 V

Storage temperature

STG

–55 100 °C

DDR2 SDRAM device operating temperature (ambient)

case

085°C

Operating temperature (ambient)

OPR

055°C

Input leakage current; Any input 0V ≤ V

IN ≤ VDD;

REF input 0V ≤ VIN ≤0.95V;

(All other pins not under test = 0V)

Command/address,

RAS#, CAS#, WE#

–80 80

µA

S#, CKE

–40 40

CK0, CK0#

–20 20

CK1, CK1#, CK2, CK2#

–30 30

–10 10

Output leakage current; 0V ≤ V

OUT ≤ VDDQ; DQ and

ODT are disabled

DQ, DQS, DQS#

–10 10 µA

REF leakage current; VREF = Valid VREF level

– –32 32 µA

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN

512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM

Electrical Specifications

Notes: 1. a = Value calculated as one module rank in this operating condition, and all other module

ranks in IDD2P (CKE LOW).

2. b = Value calculated reflects all module ranks in this operating condition.

Tabl e 7: DDR2 IDD Specifications and Conditions – 512MB

Values shown for DDR2 SDRAM components only

Parameter/Condition Symbol -667 -53E -40E Units

Operating one device bank active-precharge current;

CK =

CK (IDD),

RC =

RC (IDD),

RAS =

RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are switching; Data bus inputs are switching

DD0

680 680 640 mA

Operating one device bank active-read-precharge current; IOUT = 0mA; BL

= 4, CL = CL (I

DD), AL = 0;

CK =

CK (IDD),

RC =

RC (IDD),

RAS =

RAS MIN (IDD),

RCD =

RCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data pattern is same as IDD4W

DD1

760 760 720 mA

Precharge power-down current; All device banks idle;

CK =

CK (IDD); CKE is

LOW; Other control and address bus inputs are stable; Data bus inputs are

floating

DD2P

80 80 80 mA

Precharge quiet standby current; All device banks idle;

CK =

CK (IDD); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus

inputs are floating

DD2Q

560 560 400 mA

Precharge standby current; All device banks idle;

CK =

CK (IDD); CKE is HIGH,

S# is HIGH; Other control and address bus inputs are switching; Data bus inputs

are switching

DD2N

640 560 480 mA

Active power-down current; All device banks open;

CK =

DD); CKE is LOW; Other control and address bus inputs are

stable; Data bus inputs are floating

Fast PDN exit

MR[12] = 0

IDD3P

480 400 320 mA

Slow PDN exit

MR[12] = 1

96 96 96 mA

Active standby current; All device banks open;

CK =

CK (IDD),

RAS =

RAS

MAX (IDD),

RP =

RP (IDD); CKE is HIGH, S# is HIGH between valid commands;

Other control and address bus inputs are switching; Data bus inputs are

switching

IDD3N

800 640 480 mA

Operating burst write current; All device banks open; Continuous burst

writes; BL = 4, CL = CL (I

DD), AL = 0;

CK =

CK (IDD),

RAS =

RAS MAX (IDD),

RP =

RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs

are switching; Data bus inputs are switching

DD4W

1,560 1,320 1,040 mA

Operating burst read current; All device banks open; Continuous burst reads,

OUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;

CK =

CK (IDD),

RAS =

RAS MAX (IDD),

RP =

RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

DD4R

1,480 1,240 960 mA

Burst refresh current;

CK =

CK (IDD); REFRESH command at every

RFC (IDD)

interval; CKE is HIGH, S# is HIGH between valid commands; Other control and

address bus inputs are switching; Data bus inputs are switching

DD5

2,880 2,720 2,640 mA

Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address

bus inputs are floating; Data bus inputs are floating

IDD6

80 80 80 mA

Operating device bank interleave read current; All device banks

interleaving reads, I

OUT = 0mA; BL = 4, CL = CL (IDD), AL =

RCD (IDD) - 1 ×

DD);

CK =

CK (IDD),

RC =

RC (IDD),

RRD =

RRD (IDD),

RCD =

RCD (IDD); CKE is

HIGH, S# is HIGH between valid commands; Address bus inputs are stable during

DESELECTs; Data bus inputs are switching; See I

DD7 conditions in component

data sheet for detail

DD7

2,040 1,960 1,880 mA

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

MT16HTF25664AY-667EA3

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Manufacturer:

Micron

Description:

MODULE DDR2 SDRAM 2GB 240UDIMM

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MT16HTF25664AY-667EA3

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