Data Sheet ADIS16240
Rev. C | Page 9 of 20
BASIC OPERATION
The ADIS16240 starts up automatically when it has a valid power
supply and begins producing digital acceleration data in the output
registers. When using the factory-default configuration, DIO1
serves as a data-ready indicator signal that can drive a processor
interrupt function. Figure 14 shows a schematic for connecting
to a SPI-compatible processor platform, referred to as the SPI
master.
CS
ADIS16240
SPI SLAVE
SCLK
DIN
DOUT
DIO1
DIO2
SS
V
DD
V
DD
SYSTEM PROCESSOR
SPI MASTER
SCLK
MOSI
MISO
IRQ1
IRQ2
08133-010
Figure 14. Electrical Hook-Up Diagram
Table 5. Generic Master Processor Pin Names and Functions
Pin Name Function
SS
Slave select.
IRQ1, IRQ2 Interrupt request inputs.
MOSI Master output, slave input.
MISO Master input, slave output.
SCLK Serial clock.
The ADIS16240 SPI interface supports full duplex serial commu-
nication (simultaneous transmit and receive) and uses the bit
sequence shown in Figure 18. Processor platforms typically
support SPI communication with general-purpose serial ports that
require some configuration in their control registers. Table 6 lists
the most common settings that require attention when
initializing a pro-cessor serial port for communication with the
ADIS16240.
Table 6. Generic Master Processor SPI Settings
Processor Setting Description
Master The ADIS16240 operates as a slave.
SCLK Rate ≤ 2.5 MHz Bit rate setting.
SPI Mode 3 (1,1) Clock polarity/phase (CPOL = 1, CPHA = 1).
MSB First Bit sequence.
16-Bit Shift register/data length.
User registers govern all data collection and configuration. Table 7
provides a memory map that includes all user registers, along with
references to bit assignment tables that follow the generic assign-
ments in Figure 15.
UPPER BYTE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOWER BYTE
08133-011
Figure 15. Generic Register Bit Assignments
SPI Write Commands
Master processors write to the control registers, one byte at a
time, using the bit assignments shown in Figure 18. The program-
mable registers in Table 7 provide controls for optimizing sensor
operation and for starting various automated functions. For
example, set GLOB_CMD[8] = 1 (DIN = 0xCB01) to wake up the
device.
CS
DIN
SCLK
08133-012
Figure 16. SPI Sequence for a Wake-Up Command (DIN = 0xCB01)
Some configurations require writing both bytes to a register,
which takes two separate 16-bit sequences. See GLOB_CMD[3]
in Table 24 for backing up configuration data in nonvolatile
flash memory.
SPI Read Commands
Reading data on the SPI requires two consecutive 16-bit
sequences. The first sequence transmits the read command on
DIN, and the second sequence receives the resulting data from
DOUT. The 7-bit register address can represent either the upper
or lower byte address for the target register. For example, DIN
can be either 0x0200 or 0x0300 when reading the SUPPLY_OUT
register. The SPI operates in full duplex mode, which means that
the master processor can read the output data from DOUT while
using the same SCLK pulses to transmit a new command on
DIN. In Figure 17, the second SPI segment sets up the device to
read YACCL_OUT on the following SPI segment (not shown).
CS
DIN
SCLK
DIN = 0x0400 PRODUCES XACCL_OUT CONTENTS ON
DOUT DURING THE NEXT SPI SEGMENT
DOUT
SPI SEGMENT 1 SPI SEGMENT 2
DOUT = 0x802B = 2.21g, NEW DATA
DIN = 0x0600 TO READ YACCL_OUT
08133-013
Figure 17. Example SPI Read Sequence
ADIS16240 Data Sheet
Rev. C | Page 10 of 20
MEMORY MAP
Note that all registers are two bytes. All unused memory locations are reserved for future use.
Table 7. User Register Memory Map
Register
Name
Read/
Write
Flash
Backup
Register
Address
1
Default Function
Bit
Assignments
FLASH_CNT R Yes 0x00 N/A Flash memory write count See Table 35
SUPPLY_OUT R No 0x02 N/A Output, power supply See Table 10
XACCL_OUT R No 0x04 N/A Output, x-axis accelerometer See Table 9
YACCL_OUT
R
No
0x06
N/A
Output, y-axis accelerometer
See Table 9
ZACCL_OUT R No 0x08 N/A Output, z-axis accelerometer See Table 9
AUX_ADC R No 0x0A N/A Output, auxiliary ADC input See Table 8
TEMP_OUT R No 0x0C N/A Output, temperature See Table 11
XPEAK_OUT R No 0x0E N/A Output, x-axis acceleration peak See Table 9
YPEAK_OUT R No 0x10 N/A Output, y-axis acceleration peak See Table 9
ZPEAK_OUT R No 0x12 N/A Output, z-axis acceleration peak See Table 9
XYZPEAK_OUT R No 0x14 N/A Output, sum-of-squares acceleration peak See Table 8
CAPT_BUF1 R No
2
0x16 N/A Output, Capture Buffer 1, X and Y acceleration See Table 18
CAPT_BUF2 R No
2
0x18 N/A Output, Capture Buffer 2, Z acceleration See Table 19
DIAG_STAT R No 0x1A 0x0000 Diagnostic, error flags See Table 28
EVNT_CNTR R Yes 0x1C 0x0000 Diagnostic, event counter See Table 21
CHK_SUM R Yes 0x1E N/A Diagnostic, check sum value from firmware test See Table 34
XACCL_OFF R/W Yes 0x20 0x0000 Calibration, x-axis acceleration offset adjustment See Table 27
YACCL_OFF R/W Yes 0x22 0x0000 Calibration, y-axis acceleration offset adjustment See Table 27
ZACCL_OFF R/W Yes 0x24 0x0000 Calibration, z-axis acceleration offset adjustment See Table 27
CLK_TIME R/W Yes 0x2E 0x0000 Clock, hour and minute See Table 29
CLK_DATE
R/W
Yes
0x30
0x0000
Clock, month and day
See Table 30
CLK_YEAR R/W Yes 0x32 0x0000 Clock, year See Table 31
WAKE_TIME R/W Yes 0x34 0x0000 Wake-up setting, hour and minute See Table 32
WAKE_DATE R/W Yes 0x36 0x0000 Wake-up setting, month and day See Table 33
ALM_MAG1 R/W Yes 0x38 0x9000 Alarm 1 amplitude threshold See Table 13
ALM_MAG2
R/W
Yes
0x3A
0x9000
Alarm 2 amplitude threshold
See Table 13
ALM_CTRL R/W Yes 0x3C 0x0000 Alarm control See Table 12
XTRIG_CTRL R/W Yes 0x3E 0x0000 Capture, external trigger control See Table 15
CAPT_PNTR R/W Yes 0x40 0x0000 Capture, address pointer See Table 20
CAPT_CTRL R/W Yes 0x42 0x0022 Capture, configuration and control See Table 17
GPIO_CTRL R/W No 0x44 0x0000 General-purpose digital input/output control See Table 26
MSC_CTRL R/W No 0x46 0x0006 Miscellaneous control See Table 25
SMPL_PRD R/W Yes 0x48 0x001F Internal sample period (rate) control See Table 23
GLOB_CMD W Yes 0x4A N/A System command See Table 24
1
Each register contains two bytes. The address of the lower byte is displayed. The address of the upper byte is equal to the address of the lower byte plus 1.
2
The event capture buffer is also stored in flash, but the CAPT_BUFx registers, which only contain a single sample, are not stored in nonvolatile flash.
R/W
R/W
A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D0D1D2D3D4D5D6D7D8D9D10D11D12D13
D14
D15
NOTES
1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE, WHEN R/W = 0.
CS
SCLK
DIN
DOUT
A6 A5
D13D14D15
08133-014
Figure 18. SPI Communication Bit Sequence
Data Sheet ADIS16240
Rev. C | Page 11 of 20
OUTPUT DATA REGISTERS
Each output data register uses the bit assignments shown in
Figure 19. The ND flag indicates that unread data resides in the
register. This flag clears and returns to 0 after reading the register.
It returns to 1 after the next internal sample updates the register
with new data. When the data-ready function (the DIO1 and
DIO2 pins and the MSC_CTRL register; see Table 25) drives
data collection, the ND bit is always high and does not require
validation. The EA flag indicates that one of the error flags in the
DIAG_STAT register (see Table 28) is active (true).
MSB FOR 10-BIT OUTPUT
ND EA
x x x x D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
08133-015
Figure 19. Output Register Bit Assignments
Table 8. Output Data Register Formats
Register Bits Format Scale
SUPPLY_OUT 10 Binary, 0 V = 0x0000 4.88 mV
XACCL_OUT 10 Twos complement 51.4 mg
YACCL_OUT 10 Twos complement 51.4 mg
ZACCL_OUT 10 Twos complement 51.4 mg
AUX_ADC 10 Binary, 0 V = 0x0000 V
DD
/1024
TEMP_OUT 10 Binary, 25°C = 0x0133 0.244°C
XPEAK_OUT
1
10 Twos complement 51.4 mg
YPEAK_OUT
1
10 Twos complement 51.4 mg
ZPEAK_OUT
1
10 Twos complement 51.4 mg
XYZPEAK_OUT
2
12 Binary, 0 g
2
= 0x0000 0.676 g
2
1
Function requires MSC_CTRL[14] = 1.
2
Function requires MSC_CTRL[15] = 1.
Processing Sensor Data
Processing sensor data starts with reading the appropriate output
data register using the SPI. For example, use DIN = 0x0E00
to read the XPEAK_OUT register. Use the ND and EA bits to
validate new data and normal operating status, if necessary. Then
mask off all of the nondata bits and calculate the data, using the
format and scale information shown in Table 8. For example,
XACCL_OUT[9:0] and XYZPEAK_OUT[11:0] contain all
relevant data for their function. Table 9, Table 10, and Table 11
provide output code examples for each output register.
Table 9. Accelerometer Data Output Format
1
Binary Hex Codes Acceleration
01 0011 0111 0x137 +311 +16 g
00 0000 0010 0x002 +2 +102.8 mg
00 0000 0001 0x001 +1 +51.4 mg
00 0000 0000 0x000 0 0
11 1111 1111 0x3FF −1 51.4 mg
11 1111 1110 0x3FE −2 102.8 mg
10 1100 1001 0x2C9 311 16 g
1
The XACCL_OUT register is located at Address 0x05[15:8] and Address 0x04[7:0].
The YACCL_OUT register is located at Address 0x07[15:8] and Address 0x06[7:0].
The ZACCL_OUT register is located at Address 0x09[15:8] and Address 0x08[7:0].
The XPEAK_OUT register is located at Address 0x0F[15:8] and Address 0x0E[7:0].
The YPEAK_OUT register is located at Address 0x11[15:8] and Address 0x10[7:0].
The ZPEAK_OUT register is located at Address 0x13[15:8] and Address 0x12[7:0].
When MSC_CTRL[14] = 1, the XPEAK_OUT, YPEAK_OUT,
and ZPEAK_OUT registers track the peak acceleration in each
acceleration output register. When MSC_CTRL[15] = 1, use the
following equation to calculate the root mean square (rms) of all
three peak registers, where 1 LSB = 0.822 g:
OUTXYZPEAKXYZ
rms
_=
Set GLOB_CMD[5] = 1 to reset these registers to 0x0000.
Table 10. Power Supply Data Output Format
1
Binary Hex Codes Power Supply (V)
10 1110 0010 0x2E2 738 3.6
10 1010 0101 0x2A5 677 3.30488
10 1010 0100 0x2A4 676 3.3
10 1010 0011 0x2A3 675 3.29502
01 1110 1100 0x1EC 492 2.4
1
The SUPPLY_OUT register is located at Address 0x03[15:8] and Address 0x02[7:0].
Table 11. Temperature Data Output Format
1
Binary Hex Codes TemperatureC)
10 0010 1001 0x229 553 +85°C
01 0011 0100 0x134 308 +25.244°C
01 0011 0011 0x133 307 +25°C
01 0011 0010
0x132
306
+24.756°C
00 0010 1001 0x029 41 40°C
1
The TEMP_OUT register is located at Address 0x0D[15:8] and Address 0x0C[7:0].

ADIS16240ABCZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Accelerometers Low Pwr Prgm Impact Sensor & Recorder
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