ADIS16240ABCZ Datasheet ADIS16240ABCZ, ADIS16240/PCBZ | P13-P15

ADIS16240 Data Sheet

Rev. C | Page 12 of 20

EVENT RECORDER

The ADIS16240 provides a 3 × 8192 (8-bit) buffer memory for

capturing and storing (in flash) transient acceleration data on

all three axes (x, y, and z). There are a number of user controls for

tailoring the event recorder for optimal system-level operation.

Alarm 1 and Alarm 2 provide internal and external trigger

options for starting a data capture sequence.

Internal Trigger Setup

Select the trigger data source for Alarm 1 and Alarm 2 using

ALM_CTRL[15:8] (see Table 12). The ALM_MAG1 and ALM_

MAG2 registers contain threshold magnitude and direction

settings for Alarm 1 and Alarm 2, respectively. The format for

the data bits in these registers matches the trigger data source,

which is set using ALM_CTRL[15:8]. For example, if ALM_

CTRL[15:12] equals 0010, then the format matches that of

XACCL_OUT: 10-bit, twos complement, with 1 LSB = 51.4 mg

of acceleration.

Table 12. ALM_CTRL Register Bit Descriptions

Bit Description (Default = 0x0000)

[15:12] Alarm 2 source selection

0000 = disabled

0001 = power supply voltage (SUPPLY_OUT)

0010 = x acceleration (XACCL_OUT)

0011 = y acceleration (YACCL_OUT)

0100 = z acceleration (ZACCL_OUT)

0101 = auxiliary ADC voltage (AUX_ADC)

0110 = temperature (TEMP_OUT)

0111 = XYZ peak acceleration (XYZPEAK_OUT)

1000 = external trigger

[11:8] Alarm 1 source selection (same as Alarm 2)

[7:6] Unused

5 Alarm 2 capture trigger: 1 = enabled, 0 = disabled

4 Alarm 1 capture trigger: 1 = enabled, 0 = disabled

3 Unused

2 Alarm indicator enable: 1 = enabled, 0 = disabled

1 Alarm indicator polarity: 1 = positive, 0 = negative

0 Alarm indicator pin: 1 = DIO2, 0 = DIO1

The ALM_CTRL register is located at Address 0x3D[15:8] and Address 0x3C[7:0].

Table 13. ALM_MAG1, ALM_MAG2 Register Bit Descriptions

Bit Description (Default = 0x9000)

15 Threshold direction

1 = active for output greater than alarm magnitude

0 = inactive for output less than alarm magnitude

Unused

[13:0] Trigger threshold; bit format matches that of the register

selected by ALM_CTRL[15:8] but is unsigned.

The ALM_MAG1 register is located at Address 0x39[15:8] and Address 0x38[7:0].

The ALM_MAG2 register is located at Address 0x3B[15:8] and Address 0x3A[7:0].

Table 14. Internal Trigger Setup Example

DIN Description

0xBD44 Set Alarm 1 and Alarm 2 to ZACCL_OUT

0xB980,

0xB832

Set Alarm 1 to trigger on a measured acceleration

that has a magnitude of >2.57 g

0xBB00,

0xBA0A

Set Alarm 2 to trigger on a measured acceleration

that has a magnitude of <0.5 g

0xBC37 Activate Alarm 1 and Alarm 2 to trigger capture events,

and configure DIO2 as a positive alarm indicator output.

External Trigger Setup

ALM_CTRL[15:8] and XTRIG_CTRL (see Table 15) provide all

of the settings needed to govern the use of the comparator pins

(CMP1, CMP2) as external trigger inputs.

Table 15. XTRIG_CTRL Register Bit Descriptions

Bit

Description (Default = 0x0000)

[15:8] Unused

7 External Trigger 1 direction: 0 = <, 1 = >

6 External Trigger 2 direction: 0 = <, 1 = >

5 External Trigger 1 enable: 1 = enabled, 0 = disabled

4 External Trigger 2 enable: 1 = enabled, 0 = disabled

[3:0] External trigger-level setting (TL), binary format

Note that trigger threshold = TL × supply/24

The XTRIG_CTRL register is located at Address 0x3F[15:8] and Address 0x3E[7:0].

Table 16. External Trigger Setup Example

DIN Description

0xBD80 Set Alarm 2 to an external trigger (ALM_CTRL)

0xBE1C Activate and set CMP2 to trigger on signals that are

greater than one-half of the supply voltage (XTRIG_CTRL)

0xBC20 Activate Alarm 2 to trigger data capture (ALM_CTRL)

If the device is in standby mode, an external trigger on CMD1 or

CMD2 awakens the device and initiates an event capture. The first

sample is taken 0.2 ms + sample period (SMPL_PRD[7:0]) after

the trigger edge.

Buffer Memory Configuration

CAPT_CTRL (see Table 17) manages the buffer memory for the

event recorder using two programmable controls: event length and

pretrigger length.

Table 17. CAPT_CTRL Register Bit Descriptions

Bit Description (Default = 0x0022)

[15:8]

Unused

[7:4] Pretrigger length control factor (P), binary format

3 Unused

[2:0] Event length control factor (T), binary format

The CAPT_CTRL register is located at Address 0x43[15:8] and Address 0x42[7:0].

The event length (N

) also determines the number of events (N

)

that the buffer can store at one time.

Data Sheet ADIS16240

Rev. C | Page 13 of 20

8192

SAMPLES

EVENT 1

EVENT N

1024

= 8 × 2

EVENT 2

08133-016

Figure 20. Event Storage in Buffer Memory

For example, if CAPT_CTRL[2:0] = 100, then T = 4, which

organizes the buffer memory into 128 events of 64 samples each.

Event Organization

Each event contains a header, pretrigger data, and posttrigger data,

as shown in Figure 21. The event header provides information

about the conditions that occur when the capture takes place.

CAPT_CTRL[7:4] sets the number of pretrigger samples in

each event. If N

PRE

is negative, there is no pretrigger data and

the first sample after the trigger follows the header.



PRE

XYZPEAK_OUT

TIME

DATE

TEMP_OUT

SUPPLY_OUT

AUX_ADC

–26

–25

–1

223

–26

–25

–26

–25

255

POSTTRIGGER

DATA

PRETRIGGER

DATA

EVENT

HEADER

BUFFER 2 BUFFER 1

08133-017

Figure 21. Default Event Organization

Reading Event Data

The CAPT_BUF1, CAPT_BUF2, and CAPT_PNTR registers

manage user access to data in the capture buffer (see Table 18,

Table 19, and Table 20). The address pointer, CAPT_PNTR,

determines which capture memory location loads into the capture

buffer registers. It increments automatically with every CAPT_

BUF2 read. The most efficient method for reading the entire

buffer memory space is to alternate between the CAPT_BUF1

(DIN = 0x9600) and CAPT_BUF2 (DIN = 0x9800) read com-

mands. When alternating the read sequences in this manner,

the CAP_PNTR increments automatically and optimizes SPI

processing resources. Writing to the CAPT_PNTR register pro-

vides access to individual locations in the capture. For example,

writing 0x0138 (DIN = 0xC038, DIN = 0xC101) to the CAPT_

PNTR register causes the 311

sample in each buffer memory

to load into the CAP_BUF1 and CAPT_BUF2 locations (see

Figure 22).

Table 18. CAPT_BUF1 Register Bit Descriptions

Bit Description Format

[15:8] Y-axis acceleration

Twos complement,

205.7 mg/LSB

[7:0] X-axis acceleration

The CAPT_BUF1 register is located at Address 0x17[15:8] and Address 0x16[7:0].

Table 19. CAPT_BUF2 Register Bit Descriptions

Bit Description Format

[15:8] Unused

Twos complement,

205.7 mg/LSB

[7:0] Z-axis acceleration

The CAPT_BUF2 register is located at Address 0x19[15:8] and Address 0x18[7:0].

Table 20. CAPT_PNTR Register Bit Descriptions

Bit Description

[15:13] Unused

[7:0] Buffer address that loads into CAPT_BUF1, CAPT_BUF2

The CAPT_PNTR register is located at Address 0x41[15:8] and Address 0x40[7:0].

CAPT_PNTR

CAPT_BUF2

USER ACCESIBLE

INTERNAL MEMORY STRUCTURE

CAPT_BUF1

BUFFER 2 BUFFER 1

08133-018

Figure 22. Capture Buffer Data Flow Diagram

The EVNT_CNTR register (see Table 21) provides a running

count for the number of triggers (internal and external) that

occur after a buffer clear and/or reset. If this number is greater

than the number of events, this indicates that the device has

experienced trigger events that it could not capture because its

capture buffer is full. The EVNT_CNTR returns to 0x0000 after

a buffer clear (GLOB_CMD[6] = 1 by DIN = 0xCA40), or a

factory reset (GLOB_CMD[1] = 1 by DIN = 0xCA02). After a

power cycle or software reset command, the EVNT_CNTR

contains the number of events stored in the buffer memory.

Table 21. EVNT_CNTR Register Bit Descriptions

Bit Description

[15:0] Binary event counter

The EVNT_CNTR register is located at Address 0x1D[15:8] and Address 0x1C[7:0].

ADIS16240 Data Sheet

Rev. C | Page 14 of 20

Transient Behavior During Capture

During capture events, the device consumes an increased amount

of current for a short period. Following a capture event, sampling

suspends and the SPI commands are ignored by the sensor for

the pause times that are listed in Table 22.

Table 22. Postcapture Operation Pause Times

Event Length (Samples) Pause Time (ms)

<64 2

128 4

256 8

512 16

1024 33

OPERATIONAL CONTROL

Internal Sample Rate

The SMPL_PRD register (see Table 23) provides a user control

for sample rate adjustment, using the following equation:

)1(

32768

For example, set SMPL_PRD[7:0] = 0x07 (DIN = 0xC807) to

configure the ADIS16240 to operate at its maximum sample

rate of 4096 SPS. Note that the sample rate affects power dis-

sipation and peak resolution during event capture.

Table 23. SMPL_PRD Register Bit Descriptions

Bit Description (Default = 0x001F)

[15:0] Sample rate scale factor, binary format (N

)

The SMPL_PRD register is located at Address 0x49[15:8] and Address 0x48[7:0].

Global Commands

For convenience, the GLOB_CMD register (see Table 24) provides

an array of single-write commands. Setting the assigned bit to 1

activates each function, right after the 16

SCLK in the SPI com-

munication sequence. When the function completes, the bit

restores itself to 0. All commands in the GLOB_CMD register

require the power supply to be within normal limits for the

execution times listed in Table 24. The execution times reflect the

factory default configuration, where applicable, and describe the

time required to return to normal operation. For example, set

GLOB_CMD[2] = 1 (DIN = 0xCA04) to place the part in standby

mode. Set GLOB_CMD[8] = 1 (DIN = 0xCB01) to wake up the

device and return to normal operation.

Input/Output Lines

The ADIS16240 provides two general-purpose digital input/

output lines that offer several functions. When using the factory-

default configuration, MSC_CTRL[2:0] establishes DIO1 as

a positive data-ready output. Change MSC_CTRL[2:0] to 100

(DIN = 0xC604) to make DIO1 a negative data-ready output

signal. ALM_CTRL[2:0] offers a control for setting one of the

digital signals as an alarm indicator. For example, set ALM_

CTRL[2:0] = 110 (DIN = 0xBC06) to set DIO1 as a positive

alarm indicator output signal. When configured as general-

purpose lines, the GPIO_CTRL register configures DIO1 and

DIO2. For example, set GPIO_CTRL = 0x0103 (DIN = 0xC403,

then 0xC501) to set DIO1 and DIO2 as outputs, with DIO1 in

a 1 state and DIO2 in a 0 state. In the event of competing assign-

ments, the order of precedence is MSC_CTRL, ALM_CTRL,

and GPIO_CTRL.

Table 24. GLOB_CMD Register Bit Descriptions

Bit Description Execution Time

[15:9] Unused N/A

8 Wake up from standby mode 0.2 ms

7 Software reset 32 ms

6 Clear capture buffer flash memory 350 ms

5 Clear peak registers N/A

4 Clear DIAG_STAT register N/A

3 Save configuration to flash 24 ms

2 Start standby mode for low power N/A

1 Restore factory-default settings 350 ms

0 Auto-null N/A

The GLOB_CMD register is located at Address 0x4B[15:8] and Address 0x4A[7:0].

SPI processing and data sampling suspend for the indicated times.

Table 25. MSC_CTRL Register Bit Descriptions

Bit Description (Default = 0x0006)

15 Enables sum-of-squares output (XYZPEAK_OUT)

14 Enables peak tracking output (XPEAK_OUT,

YPEAK_OUT, and ZPEAK_OUT)

[13:10] Unused

9 No self-test on startup when set to 1

8 Self-test enable: 1 = apply electrostatic force, 0 = disabled

[7:3] Unused

2 Data-ready enable: 1 = enabled, 0 = disabled

1 Data-ready polarity: 1 = active high, 0 = active low

Data-ready line selection: 1 = DIO2, 0 = DIO1

The MSC_CTRL register is located at Address 0x47[15:8] and Address 0x46[7:0].

Table 26. GPIO_CTRL Register Bit Descriptions

Bit Description (Default = 0x0000)

[15:10] Unused

9 General-Purpose I/O Line 2 data level

8 General-Purpose I/O Line 1 data level

[7:2] Unused

1 General-Purpose I/O Line 2, data direction control:

1 = output, 0 = input

0 General-Purpose I/O Line 1, data direction control:

1 = output, 0 = input

The GPIO_CTRL register is located at Address 0x45[15:8] and Address 0x44[7:0].

Offset Adjustment

The XACCL_OUT, YACCL_OFF, and ZACCL_OFF registers

add to the sensor outputs and provide a convenient offset adjust-

ment function for each accelerometer output. For example, writing

0x0A to YACCL_OUT[7:0] (DIN = 0xA20A) results in a 514 mg

offset adjustment for the YACCL_OUT output data.

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ADIS16240ABCZ

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