isp
Lever
CORE
CORE
TM
August 2007
ipug69_01.0
Gigabit Ethernet PCS IP Core for LatticeECP2M
User’s Guide
2
Gigabit Ethernet PCS IP Core
Lattice Semiconductor for LatticeECP2M
Introduction
The 1000BASE-X physical layer, also referred to as the Gigabit Ethernet (GbE) physical layer, consists of three
major blocks, the Physical Coding Sublayer (PCS), the Physical Medium Attachment sublayer (PMA), and the
Physical Medium Dependent sublayer (PMD). The LatticeECP2M™ embedded SERDES/PCS performs the PMA
function, and portions of the PMD and PCS functions, including link serialization/deserialization, code-group align-
ment, clock tolerance compensation buffering, and 8b10b encoding/decoding. However, the embedded SER-
DES/PCS does not provide all necessary functions for implementing a complete GbE physical layer solution. That’s
where the GbE PCS IP core comes in. The IP core provides the additional functions required to fully implement the
PCS functions of the GbE physical layer. These additional functions include a transmit state machine, a receive
state machine, and auto-negotiation.
This document describes the IP core’s operation and provides instructions for generating the core through
ispLEVER
®
IPexpress™, including instantiating, synthesizing, and simulating the core.
Features
Implements the transmit, receive, and auto-negotiation functions of the IEEE 802.3z specification
8-bit GMII Interface operating at 125 MHz
8-bit Code-Group Interface operating at 125 MHz
Parallel signal interface for control and status management
Functional Description
The GbE PCS IP core converts GMII data frames into 8-bit code groups in both transmit and receive directions;
and performs auto negotiation with a link partner as described in the IEEE 802.3z specification. The core’s block
diagram is shown in Figure 1. The following paragraphs detail the operation the IP core’s main functional blocks. An
example of how this IP core may be used in implementing a gigabit ethernet physical layer is shown in Figure 2.
Figure 1. GbE PCS IP Core Block Diagram
Transmit
State Machine
Receive
State Machine
Synchronization
State Machine
Auto-Negotiation
State Machine
TxD[7:0]
Tx_CLK
Tx_Er
Tx_En
Rx_Er
Rx_Dv
Rx _Clk
RxD[7:0]
Rx_Data[7:0]
Rx_Kcntl
Rx_Even
Tx_Kcntl
Tx_Data[7:0]
MAC/PHY Mode
mr_adv_ability
mr_an_enable
mr_main_reset
mr_restart_an
mr_an_complete
mr_lp_adv_ability
mr_page_rx
GMII Interface
8-bit Code Group Interface
Signal_Detect
Rx_Disp_Err
Rx_Cv_Err
Rx_Err_Decode_Mode
Correct_Disp
Xmit_Autoneg
3
Gigabit Ethernet PCS IP Core
Lattice Semiconductor for LatticeECP2M
Figure 2. Typical GbE Physical Layer Implementation
Transmit State Machine
The transmit state machine implements the transmit functions described in clause 36 of the IEEE 802.3 specifica-
tion. The state machine’s main purpose is to convert GMII data frames into code groups. A typical timing diagram
for this circuit block is shown below. Note that the state machine in this IP core does not fully implement the conver-
sion to 10-bit code groups as specified in the 802.3 specification. Instead, partial conversion to 8-bit code groups is
performed. A separate encoder (located in the LatticeECP2M embedded SERDES/PCS block) completes the full
conversion to 10-bit code groups.
Figure 3. Typical Transmit Timing Diagram
Synchronization State Machine
The synchronization state machine implements the alignment functions described in clause 36 of the IEEE 802.3
specification. The state machine’s main purpose is to determine whether incoming code groups are properly
aligned. Once alignment is attained, proper code groups are passed to the receive state machine. If alignment is
lost for an extended period, an auto negotiation restart is triggered.
Receive State Machine
The receive state machine implements the receive functions described in clause 36 of the IEEE 802.3 specifica-
tion. The state machine’s main purpose is to convert code groups into GMII data frames. A typical timing diagram
for this circuit block is shown below. Note that the state machine in this IP core does not fully implement the conver-
sion from 10-bit code groups as specified in the 802.3 specification. Instead, partial conversion from 8-bit code
groups is performed. A separate decoder (located in the LatticeECP2M embedded SERDES/PCS block) performs
10-bit to 8-bit conversions.
User I/O
GbE
PCS
IP Core
Link State Machine
8b10b
Encoder
Decoder
SERDES
Control
Registers
MDIO
GMII 8BI
8 bits @
125 MHz
GMII
8 bits @
125 MHz
125 MHz
Ref Clk
Serial Interface
to Magnetics
or Backplane
CML
Differential Pairs
@ 1.25 Gbps
Part of Embedded
SERDES/PCS
8 bits @
125 MHz
Management
Interface
tx_d
tx_en
tx_data
tx_kcntl
preamble SFD Dest Add Src Add Len/Type Data FCS
preamble SFD Dest Add Src Add Len/Type Data FCS SPD
IDLE IDLE
EPD

GBE-PCS-PM-U1

Mfr. #:
Manufacturer:
Lattice
Description:
Programmable Logic IC Development Tools Gigabit Ethernet PCS ECP2M
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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