GBE-PCS-PM-U1

Figure 7. Configuration Dialog Box

When you click the Generate button, the IP core and supporting files are generated in the specified Project Path

directory. The directory structure of the generated files is shown in Figure 8.

Figure 8. GbE PCS IP Core Generated Directory Structure

The following files are generated at the root of the “Project Path” directory (gbe_pcs_test in Figure 8):

• <username>.lpc – IP parameter file (you may modify this file if necessary)

• <username>.ngo – Synthesized and mapped IP core

These are all of the files that you need to implement and verify the GbE PCS IP core in your own top-level design.

• <username>_generate.log – ispLEVER synthesis and map log file

The \<gbe_pcs_eval> and subtending directories provide files supporting GbE PCS core evaluation. The

\<gbe_pcs_eval> directory contains files/folders with content that is constant for all configurations of the GbE

PCS. The \<username> subfolder (\gbepcs_core0 in this example) contains files/folders with content specific

to the username configuration.

The \gbe_pcs_eval directory is created by IPexpress the first time the core is generated and updated each time

the core is regenerated. A \<username> directory is created by IPexpress each time the core is generated and

regenerated each time the core with the same file name is regenerated. A separate \<username> directory is

generated for cores with different names, e.g. \<gbepcs_core1>, \<gbepcs_core2>, etc.

name>\src\rtl\template\<technology>.

and should not be used as an actual implementation example.

The functional simulation model generated in the “Project Path” root directory (<username>_beh.v) may be

instantiated in the your testbench for evaluation in the context of your application. Lattice does not provide a test-

bench for evaluating this IP core in isolation. However, a function simulation capability is provided in which <user-

name>_beh.v is instantiated in an FPGA top level that implements a complete GbE Physical Layer as discussed

previously and described in an appendix to this document. The top-level file supporting ModelSim

provided in \<project_dir>\gbe_pc_eval\<username>\sim\modelsim. This FPGA top is instantiated in

an eval testbench provided in \<project_dir>\gbe_psc_eval\testbench.

You may run the eval simulation by doing the following:

The GbE PCS IP core itself is synthesized and is provided in NGO format when the core is generated. You may

synthesize the core in your own top-level design by instantiating the core in your top-level as described above in the

“Instantiating the Core” section and then synthesizing the entire design with either Synplicity

or Precision

RTL.

As described previously, two example RTL top-level configurations supporting GbE PCS core top-level synthesis

and implementation are provided in \<project_dir>\gbe_pcs_eval\<username>\src\rtl\top\<tech-

nology>.

name>\src\rtl\top supports the ability to implement just the GBE_PCS core. This design is intended only to

name>\src\rtl\top supports the ability to instantiate, simulate, map, place and route the GBE_PCS IP core in

LFE2M35E-6F672C device.

2. Browse to the \<project_dir\gbe_pcs_eval\<username>\impl directory and select either the

3. Select and open either <username>_reference_eval.syn or username>_core_only_eval.syn. At this

point, all of the files needed to support top-level synthesis and implementation will be imported to the project.

4. Select the device top-level entry in the left-hand GUI window.

5. Implement the complete design via the standard ispLEVER GUI flow.

Lattice’s IP hardware evaluation capability makes it possible to create versions of IP cores that operate in hardware

for a limited period of time (approximately four hours) without requiring the purchase on an IP license. The hard-

ware evaluation capability may be enabled/disabled in the Properties menu of the Build Database setup in

ispLEVER Project Navigator. It is enabled by default.

Internet: www.latticesemi.com