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Gigabit Ethernet PCS IP Core
Lattice Semiconductor for LatticeECP2M
Appendix B. GbE Physical Layer Reference Design
Introduction
This appendix describes the operation, simulation, and implementation of a GbE Physical Layer design, using Lat-
tice’s GbE PCS IP Core. The reference design utilizes two channels, one generates and monitors simplified ether-
net frames, the other loops back all received ethernet frames. The two channels can be externally connected
through the SERDES physical links, thereby establishing a demonstration of the interoperability between two GbE
physical layers. Another application is connecting the reference design loopback channel to an external GbE traffic
source (e.g. a Smartbits Test Generator), thereby demonstrating interoperability with the external traffic source.
Functional Description
The reference design block diagram is shown in Figure 9. The major blocks include two GbE PCS IP cores, the
LatticeECP2M embedded SERDES/ PCS, a frame driver, a frame receiver, and control logic.
The Driver Channel
The driver channel is shown in the lower part of Figure 9, and is comprised of a frame driver, a frame monitor, and
GbE PCS IP core, part of an embedded SERDES/PCS, and some control registers.
The transmit side of the channel begins at the frame driver, where a single 512-byte gigabit ethernet frame is
repeatedly transmitted. The frame enters the transmit side of the GbE PCS IP core, where it is converted into 8-bit
code groups. Next the frame enters the transmit portion of an embedded SERDES/PCS channel where 8b10b
encoding and 10-bit-to-1-bit serialization occurs. The frame leaves the FPGA over the external 1.25Gbps SERDES
physical link.
The receive side of the channel begins at the external SERDES input port. Clock recovery is performed, the data is
deserialized, and an 802.3z synchronization state machine aligns the data stream to comma characters, and
10B8B decoding is performed. Next the frame enters the receive portion of the GbE PCS IP core, where 8-bit code
groups are converted to GMII frames. Then the frame arrives at the frame monitor. If the payload data matches the
frame driver data pattern, a “pass” signal is asserted. If the data pattern check fails, a “fail” signal is asserted.
The Loopback Channel
The driver channel is shown in the upper part of Figure 9. It is similar to the driver channel except that it does not
contain a frame driver or frame monitor. Instead this channel utilizes a parallel loopback block. All GMII frames from
the receive path of the GbE PCS IP core are looped back to the transmit path of the GbE PCS IP core.
Clock Distribution
All timing in the reference design is derived from ref_clk a 125 MHz primary input to the FPGA. This clock is fed
to the embedded SERDES/PCS where it is phase locked and used to time all outgoing SERDES channels, used to
reference clock recovery of all incoming SERDES channels, and used to source timing for all of the FPGA soft
logic, including the transmit and receive paths of the GbE PCS IP cores.
