OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

GBE-PCS-PM-U1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
13
Gigabit Ethernet PCS IP Core
Lattice Semiconductor for LatticeECP2M
Figure 9. Block Diagram GbE Physical Layer Reference Design
IP Core Registers
A set of registers are implemented for each of the GbE PCS IP cores. These registers provide the management
control functions discussed in IEEE 802.3 clauses 22 and 37. The registers are most commonly associated with
managing auto-negotiation. The registers can be assessed by an external MDIO interface that conforms to the SMI
protocol in IEEE 802.3 clause 22 or the registers can be accessed by an external JTAG interface that conforms to
the Lattice ORCAstra protocol. The external pin enable_smi selects which register control method is used.
Table 3 shows the register set for one of the IP cores. Both IP cores have identical register sets. When using SMI,
the two cores are distinguished by using different port IDs. When using ORCAstra, the two cores are distinguished
by different memory address mappings.
SERDES/PCS
Ethernet
Physical Link
125Mhz
Ref Clk
regbus
MDIO
Registers
8b10b
Decoder
De-Serializer
8b10b
Decoder
De-Serializer
8b10b
Encoder
Serializer
8b10b
Encoder
Serializer
Link State Machine
Link State Machine
MDIO
Controller
ORCAstra
Controller
GbE PCS
IP Core
GbE PCS
IP Core
Loopback
Registers
JTAG
Frame
Driver
Frame
Monitor
regbus
SCI
SCI
SCI
8BI GMII
GMII 8BI
14
Gigabit Ethernet PCS IP Core
Lattice Semiconductor for LatticeECP2M
Table 3. GbE PCS IP Core Management Registers
LatticeECP2M Embedded SERDES/PCS Registers
The embedded SERDES/PCS has a large register set for managing control and status. These registers are auto-
matically configured for proper operation during FPGA configuration by means of an auto-configuration file called
pcs_serdes.txt. If you want the registers to maintain their auto-configured states, you do not need to manually
access the embedded SERDES/PCS registers. However, if you want to change register settings, or monitor the
status registers, then you must manually access the registers. This reference design employs an external JTAG
interface controlled by Lattice ORCAstra software for accessing the embedded SERDES/PCS registers. Table 4
shows the address mapping. Note that you may also access the GbE PCS IP core management registers through
the ORCAstra interface. Please consult technical note TN1124, LatticeECP2M SERDES/PCS Usage Guide, for
details on the embedded SERDES/PCS registers.
Table 4. ORCAstra Register Memory Map
Address
Access
Mode
Register
Name Register Bits
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0x0 R/W Control — — mr_main_reset — — mr_restart_an — — — — — — — — —
0x1 R Status 0 0 0 0 0 0 0 0 0 0 mr_an-complete 0 0 0 0 0
0x2 — N/A — — — — — — — — — — — — — — — —
0x3 — N/A — — — — — — — — — — — — — — — —
0x4 R/W
Auto-Negotiation
Advertisement
mr_adv_ability[15:0]
0x5 R
Auto-Negotiation
Link Partner
mr_lp_adv_ability[15:0]
0x6 R
Auto-Negotiation
Expansion
0 0 0 0 0 0 0 0 0 0 0 0 0 0 mr_page_rx 0
ORCAstra Address Register Description
0x000 - 0x03F Embedded SERDES/PCS – Channel 0 Registers
0x400 - 0x07F Embedded SERDES/PCS – Channel 1 Registers
0x800 - 0x0BF Embedded SERDES/PCS – Channel 2 Registers
0xC00 - 0x0FF Embedded SERDES/PCS – Channel 3 Registers
0x100 - 0x13F Embedded SERDES/PCS – Quad Registers
0x800 / 0x810 IP Core 0 / IP Core 1 – control reg [7:0]
0x801 / 0x811 IP Core 0 / IP Core 1 – control reg [15:8]
0x802 / 0x812 IP Core 0 / IP Core 1 – status reg [7:0]
0x803 / 0x813 IP Core 0 / IP Core 1 – status reg [15:8]
0x808 / 0x818 IP Core 0 / IP Core 1 – mr_adv_ability [7:0]
0x809 / 0x819 IP Core 0 / IP Core 1 – mr_adv_ability [15:8]
0x80A / 0x81A IP Core 0 / IP Core 1 – mr_lp_adv_ability [7:0]
0x80B / 0x81B IP Core 0 / IP Core 1 – mr_lp_adv_ability [15:8]
0x80C / 0x81C IP Core 0 / IP Core 1 – mr_an_expansion [7:0]
0x80D / 0x81D IP Core 0 / IP Core 1 – mr_an_expansion [15:8]
0x820 Soft FPGA Logic ID Version Register 0 (Data = 0xAA)
0x821 Soft FPGA Logic ID Version Register 1 (Data = 0x55)
0x820 Soft FPGA Logic Control Register (bit D0 enables frame driver)
15
Gigabit Ethernet PCS IP Core
Lattice Semiconductor for LatticeECP2M
Pinouts
Table shows the primary pinouts for this reference design. Note that when you choose the 672-pin package when
generating your GbE PCS IP core with Lattice IPexpress, pin-number preferences will be generated. These pin
numbers correspond to the pinouts of the Lattice demo board for ECP2M, and are listed in Table . If you choose a
different package, IPexpress will not generate a pin-out preference file, and the actual pin numbers for your design
will be chosen during place and route. In this case, the pin numbers shown in Table are not applicable.
Table 5. Reference Design Pinouts
Signal Name I/O Pin Number Description
ref_clk In N23 Reference Clock – 125 MHz clock source
rst_n In M7 Reset – Active low global reset
hdinp0 In URC_SQ_HDINP0 Inbound SERDES P – Channel 0
hdinn0 In URC_SQ_HDINN0 Inbound SERDES N – Channel 0
hdoutp0 Out URC_SQ_HDOUTP0 Outbound SERDES P – Channel 0
hdoutn0 Out URC_SQ_HDOUTN0 Outbound SERDES N – Channel 0
hdinp1 In URC_SQ_HDINP1 Inbound SERDES P – Channel 1
hdinn1 In URC_SQ_HDINN1 Inbound SERDES N – Channel 1
hdoutp1 Out URC_SQ_HDOUTP1 Outbound SERDES P – Channel 1
hdoutn1 Out URC_SQ_HDOUTN1 Outbound SERDES N – Channel 1
mdc In Note 1 MDIO Clock (0 to 50 MHz)
mdio In/Out Note 1 MDIO Bidirectional Data Signal
port_id_0[4:0] In Note 1 MDIO Port ID for IP Core 0
port_id_1[4:0] In Note 1 MDIO Port ID for IP Core 1
tck In TCK JTAG Clock Source (0 to 50 MHz)
tdi in TDI JTAG Data Input
tdo Out TDO JTAG Data Output
tms In TMS JTAG Test Mode Select
chan_0_activity_LED Out U6 Blue LED flashes when RX_DV on Chan 0 toggles
chan_0_autoneg_complete_LED Out U5 Green LED solid on when Chan0 autoneg completes OK
mon_activity_LED Out V2 Blue LED flashes when RX_DV on Chan 1 toggles
mon_autoneg_complete_LED Out W2 Green LED solid on when Chan1 autoneg completes OK
mon_pass_LED Out V1 Yellow LED solid on when Chan1 monitor data pattern OK
mon_fail_LED Out U2 Red LED solid on when Chan 1 monitor data pattern fails
enable_smi In Note 1
When high, IP core registers are controlled by MDIO.
When low, IP core registers are controlled by ORCAstra
debug_link_timer_short_0 In Note 1
When high, autoneg link timer on IP core0 is 2µsec (debug
mode).
When low, link timer on IP core0 is 10mec (normal).
debug_link_timer_short_1 In Note 1
When high, autoneg link timer on IP core1 is 2µsec (debug
mode).
When low, link timer on IP core1 is 10mec (normal)
1. Location preferences are not specified for these pins. See your implementation results for actual pin locations.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

GBE-PCS-PM-U1

Mfr. #:
Buy GBE-PCS-PM-U1
Manufacturer:
Lattice
Description:
Programmable Logic IC Development Tools Gigabit Ethernet PCS ECP2M
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet