19
LTC1736
Minimum On-Time Considerations
Minimum on-time t
ON(MIN)
is the smallest amount of time
that the LTC1736 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum on-
time limit and care should be taken to ensure that:
t
V
Vf
ON MIN
OUT
IN
()
()
<
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1736 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and voltage will increase.
The minimum on-time for the LTC1736 in a properly
configured application is generally less than 200ns. How-
ever, as the peak sense voltage decreases, the minimum
on-time gradually increases as shown in Figure 5. This is
of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre-
spondingly larger current and voltage ripple.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that is low enough
in value to provide sufficient ripple amplitude to meet the
minimum on-time requirement.
As a general rule keep the
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inductor ripple current equal or greater than 30% of
I
OUT(MAX)
at V
IN(MAX)
.
FCB Pin Operation
When the DC voltage on the FCB pin drops below its 0.8V
threshold, continuous mode operation is forced. In this
case, the top and bottom MOSFETs continue to be driven
synchronously regardless of the load on the main output.
Burst Mode operation is disabled and current reversal is
allowed in the inductor.
In addition to providing a logic input to force continuous
synchronous operation and external synchronization, the
FCB pin provides a means to regulate a flyback winding
output. During continuous mode, current flows continu-
ously in the transformer primary. The secondary winding(s)
draw current only when the bottom synchronous switch is
on. When primary load currents are low and/or the
V
IN
/V
OUT
ratio is low, the synchronous switch may not be
on for a sufficient amount of time to transfer power from
the output capacitor to the secondary load. Forced con-
tinuous operation will support secondary windings pro-
vided there is sufficient synchronous switch duty factor.
Thus, the FCB input pin removes the requirement that
power must be drawn from the inductor primary in order
to extract power from the auxiliary windings. With the loop
in continuous mode, the auxiliary output may nominally be
loaded without regard to the primary output load.
The secondary output voltage V
SEC
is normally set as
shown in the Functional Diagram by the turns ratio N of the
transformer:
V
SEC
(N + 1) V
OUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V
SEC
will droop. An external resistive divider from
V
SEC
to the FCB pin sets a minimum voltage V
SEC(MIN)
:
VV
R
R
SEC MIN()
.≈+
08 1
4
3
If V
SEC
drops below this level, the FCB voltage forces
continuous switching operation until V
SEC
is again above
its minimum.
I
L
/I
OUT(MAX)
(%)
0
MINIMUM ON-TIME (ns)
100
150
40
1736 F05
50
0
10
20
30
250
200
Figure 5. Minimum On-Time vs I
L
20
LTC1736
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.17µA
internal current source pulling the pin high. Remember to
include this current when choosing resistor values R3 and
R4.
The internal LTC1736 oscillator can be synchronized to an
external oscillator by clocking the FCB pin with a signal
above 1.5V
P-P
. When synchronized to an external fre-
quency, Burst Mode operation is disabled, but cycle skip-
ping is allowed at low load currents since current reversal
is inhibited. The bottom gate will come on every 10 clock
cycles to assure the boostrap cap, C
B
, is kept refreshed.
The rising edge of an external clock applied to the FCB pin
starts a new cycle.
The range of synchronization is from 0.9f
O
to 1.3f
O
, with
f
O
set by C
OSC
. Attempting to synchronize to a higher
frequency than 1.3f
O
can result in inadequate slope
comensation and cause loop instability with high duty
cycles. If loop instability is observed while synchronized,
additional slope compensation can be obtained by simply
decreasing C
OSC
.
The following table summarizes the possible states avail-
able on the FCB pin:
Table 2
FCB Pin Condition
DC Voltage: 0V to 0.7V Burst Disabled/Forced Continuous
Current Reversal Enabled
DC Voltage: >0.9V Burst Mode Operation, No Current Reversal
Feedback Resistors Regulating a Secondary Winding
Ext Clock: (0V to V
FCBSYNC
) Burst Mode Operation Disabled
(V
FCBSYNC
1.5V) No Current Reversal
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% - (L1 + L2 + L3 + ...)
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where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1736 circuits: 1) LTC1736 V
IN
current, 2)
INTV
CC
current, 3) I
2
R losses, 4) Topside MOSFET transi-
tion losses.
1. The V
IN
current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. V
IN
current results in a small
(<0.1%) loss that increases with V
IN
.
2. INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTV
CC
to ground. The resulting dQ/dt is a current
out of INTV
CC
that is typically much larger than the
control circuit current. In continuous mode, I
GATECHG
=
f(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges of the
topside and bottom-side MOSFETs.
Supplying INTV
CC
power through the EXTV
CC
switch
input from an output-derived or other high efficiency
source will scale the V
IN
current required for the driver
and control circuits by a factor of (Duty Cycle)/(Effi-
ciency). For example, in a 15V to 1.8V application, 10mA
of INTV
CC
current results in approximately 1.2mA of V
IN
current. This reduces the low current loss from 10% or
more (if the driver was powered directly from V
IN
) to only
a few percent.
3. I
2
R Losses are predicted from the DC resistances of the
MOSFETs, inductor and current shunt. In continuous
mode the average output current flows through L and
R
SENSE
, but is “chopped” between the topside main
MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same R
DS(ON)
, then
the resistance of one MOSFET can simply be summed
with the resistances of L and R
SENSE
to obtain I
2
R
losses. For example, if each R
DS(ON)
= 0.02, R
L
=
0.03, and R
SENSE
= 0.01, then the total resistance is
21
LTC1736
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0.06. This results in losses ranging from 3% to 17%
as the output current increases from 1A to 5A for a 1.8V
output, or 4% to 20% for a 1.5V output. Efficiency
varies as the inverse square of V
OUT
for the same
external components and power level. I
2
R losses cause
the efficiency to drop at high output currents.
4. Transition losses apply only to the topside MOSFET(s),
and only become significant when operating at high
input voltages (typically 12V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7)(V
IN
2
)(I
O(MAX)
)(C
RSS
)(f)
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and fuse resis-
tance losses can be minimized by making sure that C
IN
has
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having a maxi-
mum of 0.01 to 0.02 of ESR. Other losses including
Schottky conduction losses during dead-time and induc-
tor core losses generally account for less than 2% total
additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal to I
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. I
LOAD
also begins to charge or
discharge C
OUT
generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recovery
time V
OUT
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the I
TH
pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed-loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed-loop response. Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I
TH
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.
The I
TH
series R
C
-C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full-load current having a rise time of 1µs
to 10µs will produce output voltage and I
TH
pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step
may not be within the bandwidth of the feedback loop, so
the standard second-order overshoot/DC ratio cannot be
used determine phase margin. The gain of the loop will be
increased by increasing R
C
and the bandwidth of the loop
will be increased by decreasing C
C
. If R
C
is increased by the
same factor that C
C
is decreased, the zero frequency will
be kept the same, thereby keeping the phase the same in
the most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability of
the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Application Note 76.
Improve Transient Response and Reduce Output
Capacitance with Active Voltage Positioning
Fast load transient response, limited board space and low
cost are requirements of microprocessor power supplies.
Active voltage positioning improves transient response
and reduces the output capacitance required to power a
microprocessor where a typical load step can be from 0.2A

LTC1736IG#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 5-B Adj Hi Eff Sync Buck Sw Reg
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