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LTC1736IG#PBF

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22
LTC1736
to 15A in 100ns or 15A to 0.2A in 100ns. The voltage at the
microprocessor must be held to about ±0.1V of nominal
in spite of these load current steps. Since the control loop
cannot respond this fast, the output capacitors must
supply the load current until the control loop can respond.
Capacitor ESR and ESL primarily determine the amount of
droop or overshoot in the output voltage. Normally, sev-
eral capacitors in parallel are required to meet micropro-
cessor transient requirements.
Active voltage positioning is a form of deregulation. It
sets the output voltage high for light loads and low for
heavy loads. When load current suddenly increases, the
output voltage starts from a level higher than nominal so
the output voltage can droop more and stay within the
specified voltage range. When load current suddenly
decreases the output voltage starts at a level lower than
nominal so the output voltage can have more overshoot
and stay within the specified voltage range. Less output
capacitance is required when voltage positioning is used
because more voltage variation is allowed on the output
capacitors.
Active voltage positioning can be implemented using the
OPTI-LOOP architecture of the LTC1736 with two external
resistors. An input voltage offset is introduced when the
error amplifier has to drive a resistive load. This offset is
limited to ±30mV at the input of the error amplifier. The
resulting change in output voltage is the product of input
offset and the feedback voltage divider ratio.
Figure 6 shows a CPU-core-voltage regulator with active
voltage positioning. Resistors R1 and R5 force the input
voltage offset that sets the output voltage according to the
load current level. To select values for R1 and R5, first
determine the amount of output deregulation allowed. The
actual specification for a typical microprocessor allows
the output to vary ±0.112V. The LTC1736 output voltage
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
C
OSC
RUN/SS
I
TH
FCB
SGND
PGOOD
SENSE
–
SENSE
+
V
FB
V
OSENSE
VID0
VID1
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
VIDV
CC
VID4
VID3
VID2
LTC1736
C5
1000pF
C6
47pF
VID0
VID1
VID2
VID3
VID4
VID
INPUT
C7 330pF
C3
100pF
C1 39pF
C4 100pF
C2
0.1µF
POWER
GOOD
R2
100k
R5
100k
R4
100k
R3
680k
R1
27k
+
C10
1µF
5V (OPTIONAL)
C18
1µF
C12 TO C14
10µF
35V
C11
4.7µF
10V
D1
CMDSH-3
C8
0.1µF
D2
MBRS340
C9
0.22µF
M1
FDS6680A
L1
1µH
R6
0.003Ω
M2, M3
FDS6680A
×2
1736 F06
C15 TO C17
180µF/4V
×4
V
OUT
0.9V TO 2V
15A
GND
GND
V
IN
7.5V TO 24V
+
C10, C18: TAIYO YUDEN JMK107BJ105
C11: KEMET T494A475M010AS
C12 TO C14: TAIYO YUDEN GMK325F106
C15 TO C17: PANASONIC EEFUE0G181R
D1: CENTRAL SEMI CMDSH-3
D2: MOTOROLA MBRS340
L1: PANASONIC ETQP6F1R0SA
M1 TO M3: FAIRCHILD FDS6680A
R6: IRC LRF2512-01-R003-J
U1: LINEAR TECHNOLOGY LTC1736CG
Figure 6. CPU-Core-Voltage Regulator with Active Voltage Positioning
APPLICATIO S I FOR ATIO
WUU
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23
LTC1736
accuracy is ±1%, so the output transient voltage cannot
exceed ±0.097V. At V
OUT
= 1.5V, the maximum output
voltage change controlled by the I
TH
pin would be:
∆=
=
±
=±
V
Input Offset V
V
V
V
mV
OSENSE
OUT
REF
•
.•.
.
003 15
08
56
With optimum resistor values at the I
TH
pin, the output
voltage will swing from 1.55V at minimum load to 1.44V
at full load. At this output voltage, active voltage position-
ing provides an additional 56mV to the allowable transient
voltage on the output capacitors, a 58% improvement
over the 97mV allowed without active voltage positioning.
The next step is to calculate the I
TH
pin voltage, V
ITH
, scale
factor. The V
ITH
scale factor reflects the I
TH
pin voltage
required for a given load current. V
ITH
controls the peak
sense resistor voltage, which represents the DC output
current plus one half of the peak-to-peak inductor current.
The no load to full load V
ITH
range is from 0.3V to 2.4V,
which controls the sense resistor voltage from 0V to the
∆V
SENSE(MAX)
voltage of 75mV. The calculated V
ITH
scale
factor with a 0.003Ω sense resistor is:
V ScaleFactor
V Range Sense sistor Value
V
VV
V
VA
ITH
ITH
SENSE MAX
=
∆
==
•Re
(. – . )• .
.
./
()
24 03 0003
0 075
0 084
V
ITH
at any load current is:
VI
I
V ScaleFactor
V Offset
ITH OUT DC
L
ITH
ITH
=+
∆
+
()
•
2
At full load current:
VA
A
VA V
V
ITH MAX
PP
()
•. / .
.
=+
+
=
−
15
5
2
0 084 0 3
177
At minimum load current:
VA
A
VA V
V
ITH MIN
PP
()
.•./.
.
=+
+
=
−
02
2
2
0 084 0 3
040
In this circuit, V
ITH
changes from 0.40V at light load to
1.77V at full load, a 1.37V change. Notice that ∆I
L
, the
peak-to-peak inductor current, changes from light load to
full load. Increasing the DC inductor current decreases the
permeability of the inductor core material, which de-
creases the inductance and increases ∆I
L
. The amount of
inductance change is a function of the inductor design.
To create the 30mV input offset, the gain of the error
amplifier must be limited. The desired gain is:
A
V
Input Offset
V
V
V
ITH
=
∆
==
137
2003
22 8
.
(. )
.
Connecting a resistor to the output of the transconductance
error amplifier will limit the voltage gain. The value of this
resistor is:
R
A
Error Amplifier g ms
k
ITH
V
m
===
22 8
13
17 54
.
.
.
To center the output voltage variation, V
ITH
must be
centered so that no I
TH
pin current flows when the output
voltage is nominal. V
ITH(NOM)
is the average voltage be-
tween V
ITH
at maximum output current and minimum
output current:
V
VV
V
VV
VV
ITH NOM
ITH MAX ITH MIN
ITH MIN()
() ()
()
–
.–.
..
=+
=+=
2
177 040
2
0 40 1 085
The Thevenin equivalent of the gain limiting resistance
value of 17.54k is made up of a resistor R5 that sources
current into the I
TH
pin and resistor R1 that sinks current
to SGND.
APPLICATIO S I FOR ATIO
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24
LTC1736
V
IN
= 12V
V
OUT
= 1.5V
1.5V
100mV/DIV
15A
0A
10A/DIV
OUTPUT
VOLTAGE
LOAD
CURRENT
50µs/DIV
1736 F07
Figure 7. Normal Transient Response (Without R1, R5)
V
IN
= 12V
V
OUT
= 1.5V
1.582V
1.5V
1.418V
100mV/DIV
15A
0A
10A/DIV
50µs/DIV
1736 F08
Figure 8. Transient Response with Active Voltage Positioning
OUTPUT
VOLTAGE
LOAD
CURRENT
To calculate the resistor values, first determine the ratio
between them:
k
VV
V
VV
V
INTVCC ITH NOM
ITH NOM
===
–
.–.
.
.
()
()
52 1085
1 085
379
V
INTVCC
is equal to V
EXTVCC
or 5.2V if EXTVCC is not used.
Resistor R5 is:
Rk R k k
ITH
4 1 3 79 1 17 54 84 0=+ = + =()• (. )•. .
Resistor R1 is:
R
kR
k
k
k
ITH
1
1 3 79 1 17 54
379
22 17=
+
=
+
=
()• (. )•.
.
.
Unfortunately, PCB noise can add to the voltage developed
across the sense resistor, R6, causing the ITH pin voltage
to be slightly higher than calculated for a given output
current. The amount of noise is proportional to the output
current level. This PCB noise does not present a serious
problem but it does change the effective value of R6 so the
calculated values of R1 and R5 may need to be adjusted to
achieve the required results. Since PCB noise is a function
of the layout, it will be the same on all boards with the same
layout.
Figures 7 and 8 show the transient response before and
after active voltage positioning is implemented. Notice
that the output voltage droop and overshoot levels don’t
change but the peak-to-peak output voltage reduces con-
siderably with active voltage positioning.
Refer to Design Solutions 10 for more information about
active voltage positioning.
Automotive Considerations:
Plugging into the Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main power line in an automobile
is the source of a number of nasty potential transients,
including load dump, reverse battery, and double battery.
Load dump is the result of a loose power cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 9 is the most straight forward
approach to protect a DC/DC converter from the ravages
of an automotive power line. The series diode prevents
current from flowing during reverse battery, while the
transient suppressor clamps the input voltage during load
dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamp the input voltage below breakdown of the converter.
Although the LTC1736 has a maximum input voltage of
36V, most applications will be limited to 30V by the
MOSFET BV
DSS
.
APPLICATIO S I FOR ATIO
WUU
U
FIGURE 6 CIRCUIT
FIGURE 6 CIRCUIT
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LTC1736IG#PBF

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Buy LTC1736IG#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 5-B Adj Hi Eff Sync Buck Sw Reg
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