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LTC1736IG#PBF

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7
LTC1736
PI FU CTIO S
UUU
C
OSC
(Pin 1): External capacitor C
OSC
from this pin to
ground sets the operating frequency.
RUN/SS (Pin 2): Combination of Soft-Start and Run
Control Inputs. A capacitor to ground at this pin sets the
ramp time to full output current. The time is approximately
1.25s/µF. Forcing this pin below 1.5V causes the device to
be shut down. In shutdown all functions are disabled.
Latchoff overcurrent protection is also invoked via this pin
as described in the Applications Information section.
I
TH
(Pin 3): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 2.4V.
FCB (Pin 4): Forced Continuous/Synchronization Input.
Tie this pin to ground for continuous synchronous opera-
tion, to a resistive divider from the secondary output when
using a secondary winding, or to INTV
CC
to enable Burst
Mode operation at low load currents. Clocking this pin with
a signal above 1.5V
P-P
disables Burst Mode operation but
allows cycle skipping at low load currents and synchro-
nizes the internal oscillator with the external clock.
SGND (Pin 5): Small-Signal Ground. All small-signal
components such as C
OSC
, C
SS
plus the loop compensa-
tion resistors and capacitor(s) should single-point tie to
this pin. This pin should, in turn, connect to PGND.
PGOOD (Pin 6): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage on the V
OSENSE
pin is
not within ±7.5% of its set point.
SENSE
–
(Pin 7): The (–) Input to the Current Comparator.
SENSE
+
(Pin 8): The (+) Input to the Current Comparator.
Built-in offsets between SENSE
–
and SENSE
+
pins in
conjunction with R
SENSE
set the current trip threshold.
V
FB
(Pin 9): Divided Down V
OSENSE
Voltage Feeding the
Error Amplifier of the Regulator. The VID inputs program
a resistive divider between V
OSENSE
and SGND; the tap
point on the divider is V
FB
. The voltage on V
FB
is 0.8V when
the output is in regulation. This pin can be bypassed to
SGND with 50pF to 100pF.
V
OSENSE
(Pin 10): Receives the remotely sensed feedback
voltage from the output.
VID0 to VID4 (Pins 11 to 15): Digital Inputs for controlling
the output voltage from 0.925V to 2.0V. Table 1 specifies
the V
OSENSE
voltages for the 32 combinations of digital
inputs. The LSB (VID0) represents 50mV increments in
the upper voltage range (2.00V to 1.30V) and 25mV
increments in the lower voltage range (1.275V to 0.925V).
Logic Low = GND, Logic High = VIDV
CC
or Float.
VIDV
CC
(Pin 16): VID Input Supply Voltage. Can range
from 2.7V to 7V. Typically this pin is tied to INTV
CC
.
EXTV
CC
(Pin 17): Input to the Internal Switch Connected
to INTV
CC
. This switch closes and supplies V
CC
power
whenever EXTV
CC
is higher than 4.7V. See EXTV
CC
con-
nection in the Applications Information section. Do not
exceed 7V to this pin and ensure EXTV
CC
≤ V
IN
.
PGND (Pin 18): Driver Power Ground. This pin connects
to the source of the bottom N-channel MOSFET, the anode
of the Schottky diode and the (–) terminal of C
IN
.
BG (Pin 19): High Current Gate Drive for Bottom
N-Channel MOSFET. Voltage swing at this pin is from
ground to INTV
CC
.
INTV
CC
(Pin 20): Output of the Internal 5.2V Regulator and
EXTV
CC
Switch. The driver and control circuits are pow-
ered from this voltage. Decouple to power ground with a
1µF ceramic capacitor placed directly adjacent to the IC
together with a minimum of 4.7µF tantalum or other low
ESR capacitor.
V
IN
(Pin 21): Main Supply Pin. This pin must be closely
decoupled to power ground.
SW (Pin 22): Switch Node Connection to Inductor and
Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground to
V
IN
.
BOOST (Pin 23): Supply to Topside Floating Driver. The
bootstrap capacitor is returned to this pin. Voltage swing
at this pin is from a diode drop below INTV
CC
to V
IN
+
INTV
CC
.
TG (Pin 24): High Current Gate Drive for Top N-Channel
MOSFET. This is the output of a floating driver with a
voltage swing equal to INTV
CC
superimposed on the
switch node voltage SW.
8
LTC1736
FU CTIO AL DIAGRA
UU
W
OPERATIO
U
(Refer to Functional Diagram)
Main Control Loop
The LTC1736 uses a constant frequency, current mode
step-down architecture. During normal operation, the
top MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the main current
comparator I1 resets the RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
voltage on Pin I
TH
, which is the output of the error
amplifier EA. Pin V
OSENSE
, described in the Pin Functions,
allows EA to receive an output feedback voltage V
FB
from
the internal resistive divider. When the load current
increases, it causes a slight decrease in V
FB
relative to the
0.8V reference, which in turn causes the I
TH
voltage to
increase until the average inductor current matches the
new load current. While the top MOSFET is off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current com-
parator I2, or the beginning of the next cycle.
The top MOSFET driver is powered from a floating
bootstrap capacitor C
B
. This capacitor is normally re-
charged from INTV
CC
through an external Schottky diode
when the top MOSFET is turned off. As V
IN
decreases
towards V
OUT
, the converter will attempt to turn on the
top MOSFET continuously (‘’dropout’’). A dropout counter
detects this condition and forces the top MOSFET to turn
off for about 500ns every tenth cycle to recharge the
bootstrap capacitor.
SW
–
+
+
–
0.86V
0.74V
–
+
0.55V
2.4V
0.8V
47pF
0.86V
I1
+
–
I2
+
–
EA
A
BURST
DISABLE
FC
OV
B
–
+
4.8V
IREV
+
–
+
–
F
FC
S
R
Q
DROP
OUT
DET
0.8V
REF
SWITCH
LOGIC
SD
6V
RUN/SS
C
SS
R
C
V
FB
40k
1.2µA
RUN
SOFT
START
+
OVER-
CURRENT
LATCH-OFF
SD
I
TH
C
C
0.17µA
OSC
4(V
FB
)
BUFFERED
I
TH
SLOPE COMP
+– –+
3mV
ICMP
R2
10k
R1
SGND
V
FB
V
OSENSE
2k
45k
BOT
TOP ON
FORCE BOT
45k
30k 30k
SENSE
+
SENSE
–
SYNC
1.2V 0.8V
C
TOP
UVL
BOT
INTV
CC
5.2V
LDO
REG
V
IN
+
C
INTVCC
V
OUT
V
SEC
INTV
CC
BG
PGND
V
IN
V
IN
BOOST
TG
INTV
CC
C
B
D
B
D
1
C
OSC
+
C
IN
+
C
SEC
•
•
+
C
OUT
EXTV
CC
FCB
R4
R3
C
OSC
R
SENSE
1736 FD
1
PGOOD
6
9
10
5
VIDV
CC
VID4
INTV
CC
15
VID3
14
VID2
13
VID1
12
VID0
11
4
21
23
24
22
20
19
18
17783
2
–
+
VID
DECODER
16
g
m
=1.3m
Ω
9
LTC1736
OPERATIO
U
(Refer to Functional Diagram)
The main control loop is shut down by pulling Pin 2 (RUN/
SS) low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor C
SS
. When
C
SS
reaches 1.5V, the main control loop is enabled with the
I
TH
voltage clamped at approximately 30% of its maximum
value. As C
SS
continues to charge, I
TH
is gradually re-
leased allowing normal operation to resume. If V
OUT
has
not reached 70% of its final value when C
SS
has charged
to 4.1V, latchoff can be invoked as described in the
Applications Information section.
The internal oscillator can be synchronized to an external
clock applied to the FCB pin and can lock to a frequency
between 90% and 130% of its nominal rate set by capaci-
tor C
OSC
.
An overvoltage comparator OV guards against transient
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned on
until the overvoltage condition is cleared.
Foldback current limiting for an output shorted to ground
is provided by amplifier A. As V
FB
drops below 0.6V, the
buffered I
TH
input to the current comparator is gradually
pulled down to a 0.86V clamp. This reduces peak inductor
current to about 1/4 of its maximum value.
Low Current Operation
The LTC1736 has three low current modes controlled by
the FCB pin. Burst Mode operation is selected when the
FCB pin is above 0.8V (typically tied to INTV
CC
). During
Burst Mode operation, if the error amplifier drives the I
TH
voltage below 0.86V, the buffered I
TH
input to the current
comparator will be clamped at 0.86V. The inductor current
peak is then held at approximately 20mV/R
SENSE
(about 1/
4 of maximum output current). If I
TH
then drops below
0.5V, the Burst Mode comparator B will turn off both
MOSFETs to maximize efficiency. The load current will be
supplied solely by the output capacitor until I
TH
rises
above the 60mV hysteresis of the comparator and switch-
ing is resumed. Burst Mode operation is disabled by
comparator F when the FCB pin is brought below 0.8V.
This forces continuous operation and can assist second-
ary winding regulation.
When the FCB pin is driven by an external oscillator, a low
noise cycle-skipping mode is invoked and the internal
oscillator is synchronized to the external clock by com-
parator C. In this mode the 25% minimum inductor
current clamp is removed, providing constant frequency
discontinuous operation over the widest possible output
current range. This constant frequency operation is not
quite as efficient as Burst Mode operation, but provides a
lower noise, constant frequency spectrum.
The FCB pin is tied to ground when forced continuous
operation is desired. This operation is the least efficient
mode, but is desirable in certain applications. The output
can source or sink current in this mode. When sinking
current while in forced continuous operation, current will
be forced back into the main power supply potentially
boosting the input supply to dangerous voltage levels—
BEWARE.
Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff
The RUN/SS capacitor, C
SS
, is used initially to limit the
inrush current of the switching regulator. After the con-
troller has been started and been given adequate time to
charge up the output capacitors and provide full load
current, C
SS
is used as a short-circuit time-out circuit. If
the output voltage falls to less than 70% of its nominal
output voltage, C
SS
begins discharging on the assumption
that the output is in an overcurrent and/or short-circuit
condition. If the condition lasts for a long enough period
as determined by the size of the C
SS
, the controller will be
shut down until the RUN/SS pin voltage is recycled. This
built-in latchoff can be overridden by providing a current
>5µA at a compliance of 5V to the RUN/SS pin. This
current shortens the soft-start period but also prevents net
discharge of C
SS
during an overcurrent and/or short-
circuit condition. Foldback current limiting is activated
when the output voltage falls below 70% of its nominal
level whether or not the short-circuit latchoff circuit is
enabled.
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LTC1736IG#PBF

Mfr. #:
Buy LTC1736IG#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 5-B Adj Hi Eff Sync Buck Sw Reg
Lifecycle:
New from this manufacturer.
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