Data Sheet ADRF5132
Rev. A | Page 5 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12
11
10
1
3
4
9
2
6
5
7
8
16
15
14
13
GND
RF1
NIC
GND
GND
GND
V
CTL
GND
V
DD
RF2
NIC
GND
GND
RFC
GND
GND
ADRF5132
TOP VIEW
(Not to Scale)
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT
CONNECTED INTERNALLY; HOWEVER, ALL DATA SHOWN
HEREIN WAS MEASURED WITH THESE PINS CONNECTED
TO RF/DC GROUND EXTERNALLY.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED
TO RF/DC GROUND.
16424-002
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 4, 5, 6, 8, 9, 12, 13, 15 GND Ground. See Figure 3 for the GND interface schematic.
2 RF1 RF Port 1. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
3, 10 NIC Not Internally Connected. These pins are not connected internally; however, all data shown herein
was measured with these pins connected to RF/dc ground externally.
7 RFC RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required
on this pin.
11 RF2 RF Port 2. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
14 V
CTL
Control Input. See Figure 4 for the V
CTL
interface schematic. Refer to Table 5 and the recommended
digital input control voltage range in Table 1.
DD
EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground.
Table 5. Truth Table
Signal Path State
Control Input, V
CTL
State RFC to RF1 RFC to RF2
High Off On
Low On Off
INTERFACE SCHEMATICS
Figure 3. Ground Interface
Figure 4. Control Interface