FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
10 REVISION B 7/29/16
TABLE 5B. AC CHARACTERISTICS, V
CC
= V
CCO
= 3.3V±5%, V
EE
= 0V, TA = -40°C TO 85°C (VC = 1, VCXO MODE)
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fosc XTAL Frequency 30.72 MHz
f
OUT
Output Frequency;
NOTE 1
QAx, QBx, QC
nBYPASS = 1, MF = 20, N = 1 614.4 MHz
nBYPASS = 1, MF = 20, N = 4 153.6 MHz
nBYPASS = 1, MF = 20, N = 5 122.88 MHz
nBYPASS = 1, MF = 20, N = 20 30.72 MHz
nBYPASS = 1, MF = 16, N = 1 491.52 MHz
nBYPASS = 1, MF = 16, N = 4 122.88 MHz
nBYPASS = 1, MF = 16, N = 5 98.304 MHz
nBYPASS = 1, MF = 16, N = 20 24.576 MHz
APR Absolute Pull Range -50 50 ppm
BW Modulation Bandwidth of VCXO 200 kHz
L
VC
Tuning Linearity VC = 0.6V to 1.4V ±6.5 %
tjit(Ø)
RMS Phase Jitter;
Integration Range: 12kHz - 20MHz
f
OUT
= 122.88MHz,
XTAL = 30.72MHz
0.88 ps/rms
F
n
Single-Side Band
Phase Noise at
f
OUT
= 122.88MHz
10Hz offset
XTAL = 30.72MHz
-41.18 dBc/Hz
100Hz offset -72.82 dBc/Hz
1kHz offset -104.19 dBc/Hz
10kHz offset -126.63 dBc/Hz
100kHz offset -128.57 dBc/Hz
spurious Does not include harmonic spurs -51 dB
sub harmonics -11 dB
tsk(o)
Output Skew;
NOTE 2
f
QA
= f
QB
= f
QC
240 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 160 700 ps
odc Output Duty Cycle
N 1
45 55 %
N = 1 40 60 %
NOTE 1: f
OUT
= ((30.72MHz) * MF) ÷ N ± 50ppm.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
REVISION B 7/29/16
813076 DATA SHEET
11 FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
SCOPE
Qx
nQx
LVPECL
V
EE
V
CC,
V
CCO
V
CCA
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
DIFFERENTIAL INPUT LEVEL
2V
-1.3V ± 0.165V
2V
SPURIOUS/SUB-HARMONICS
Sub-harmonic
Spurious
Frequency
Spectral Power
-3 f
OUT
-2 f
OUT
2 f
OUT
3 f
OUT
f
OUT
QAx,
QBx, QC
nQAx,
nQBx, nQC
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
12 REVISION B 7/29/16
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The ICS813076I
provides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V
CC
, V
CCA
, and
V
CCO
should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be
used for each pin. Figure 3 illustrates this for a generic V
CC
pin
and also shows that V
CCA
requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the V
CCA
pin.
FIGURE 3. POWER SUPPLY FILTERING
10Ω
V
CCA
10 μF
.01μF
3.3V
.01μF
V
CC
FIGURE 4. SINGLE-ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 4 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V and R2/
R1 = 0.609.
V_REF
Single Ended Clock Input
V
CC
CLKx
nCLKx
R1
1K
C1
0.1u R2
1K

813076CYILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner VCXO FEMTOCLOCK JITTER ATTENUATION
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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