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813076CYILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
4 REVISION B 7/29/16
f
IN
(MHz) f
OUT
(MHz) Ratio
Confi guration
P MV MF NA, NB, NC
30.72 30.72 1 1 1 20 20
30.72 122.8 4 1 1 20 5
30.72 153.6 5 1 1 20 4
30.72 614.4 20 1 1 20 1
30.72 24.576 4/5 1 1 16 20
30.72 98.304 16/5 1 1 16 5
30.72 122.8 4 1 1 16 4
30.72 491.52 16 1 1 16 1
NOTE: The example frequency confi guration table is intended to show the most common fre-
quency translations. The following example will illustrate the confi guration process.
TABLE 3A. FREQUENCY CONFIGURATION EXAMPLES TABLE (f
VCXO
= 30.72MHZ)
DEVICE CONFIGURATION
The ICS813076I is a two stage device, a VCXO PLL stage followed
by a low phase noise FemtoClock PLL multiplier stage. The VCXO
PLL stage uses a pullable crystal to lock to the reference clock. The
low phase noise FemtoClock multiplies the VCXO PLL output clock
up to 614.4MHz and three independent output dividers scale the
frequency down to the desired output frequencies. With a given input
and VCXO frequency, the output frequency is a function of the P, MV,
MF and NA, NB, NC dividers, and can be set by pulling confi guration
pins high or low. See “ICS813076I Examples Frequency Con-
fi guration (f
VCXO
= 30.72MHz)” for typical device confi gurations. Note
that for correct operation, the input frequency times the MV-divider
must be 30.72MHz ± 50ppm. The ICS813076I supports up to three
output frequencies f
OUT
independently.
30.72MH z
XTALIN XTALOUT
30.72MHz
VCXO
MV = 1
P = 1
FemtoClock PLL
VCO = 614.4MHz
MF = 20
N = 4
153.6MHz
Qn
CLK
ICS813076I
FIGURE 1. APPLICATION EXAMPLE (153.6MHZ CLOCK GENERATION AND JITTER ATTENUATION)
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
R
PULLUP
Input Pullup Resistor 51 kΩ
R
PULLDOWN
Input Pulldown Resistor 51 kΩ
REVISION B 7/29/16
813076 DATA SHEET
5 FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
TABLE 3B. VCXO PRE-DIVIDER (P) CONFIGURATION TABLE
Input
Pre-Divider Function OperationP_SEL
0÷1f
PD
= f
REF
÷ 1
1÷2f
PD
= f
REF
÷ 2
Input
OperationREF_SEL
0 (default) Selects CLK0, nCLK0 as PLL reference signal
1 Selects CLK1, nCLK1 as PLL reference signal
TABLE 3C. VCXO MULTIPLIER (MV-DIVIDER) CONFIGURATION TABLE
Input
Multiplier MV Function OperationMV_SEL
01f
VCXO
= f
PD
12f
VCXO
= f
PD
* 2
The VCXO pre-divider (P) down-scales the input reference
frequency f
REF
and enables the use of the ICS813076I at a variety
of input frequencies. P_SEL and MV_SEL must be set to match the
VCXO frequency: f
REF
÷ P = f
VCXO
÷ MV. For instance, at the nominal
VCXO frequency of 30.72MHz and if MV equals two, the input
frequency must be an integer multiple of 15.36MHz.
TABLE 3F. PLL OUTPUT-DIVIDER (NA, NB, NC) CONFIGURATION TABLE
TABLE 3E. INPUT REFERENCE CLOCK MULTIPLEXER
CONFIGURATION TABLE
Inputs
Output Dividers
NA, NB, NC OperationNx_SEL1 Nx_SEL0
0 0 ÷1 f
OUT
= f
VCO
0 1 ÷4 f
OUT
= f
VCO
÷ 4
1 0 ÷5 f
OUT
= f
VCO
÷ 5
1 1 ÷20 f
OUT
= f
VCO
÷ 20
The FemtoClock PLL stage multiplies the VCXO frequency (30.72MHz) to
491.52MHz or 614.4MHz. The output frequency equals:
[(f
REF
÷ P) * MV * MF] ÷ N. The NA, NB and NC dividers operate independently.
TABLE 3D. FEMTOCLOCK FEEDBACK DIVIDER (MF)
CONFIGURATION TABLE
Input
Multiplier MF Function OperationMF_SEL
020f
VCO
= f
VCXO
* 20
116f
VCO
= f
VCXO
* 16
TABLE 3G. PLL BYPASS CONFIGURATION TABLE
Input
OperationnBYPASS
0
f
OUT
= f
REF
÷ N
VCXO and PLL bypassed, no jitter attenuation and frequency multiplication. AC specifi cations do not apply.
1 (default)
((f
REF
÷ P) * MV * MF) ÷ N
VCXO and PLL operation, jitter attenuation and frequency multiplication enabled.
The nBYPASS control should be set to logic HIGH for normal operation. nBYPASS = 0 enables the PLL bypass mode for factory test.
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
6 REVISION B 7/29/16
TABLE 3H. FAST LOCK MODE CONFIGURATION TABLE
Input
OperationFLM
0 (default) Normal operation.
1
Fast PLL lock operation. Use this mode only
during start-up to decrease PLL lock time.
TABLE 3I. RESET AND OUTPUT CONFIGURATION TABLE
Input
OperationnMR
0 The Femto-PLL is reset.
1 (default) Normal operation and outputs are enabled.
TABLE 3J. RESET AND OUTPUT CONFIGURATION T ABLE
Input
OperationnSTOP
0
QA[4:0], QB[2:0] and QC outputs are stopped in logic LOW state. nQA[4:0], nQB[2:0] and nQC outputs are stopped
in logic HIGH state (QX = LOW, nQX = HIGH). The assertion of nSTOP is asynchronous to the internal clock signal
and may cause an output runt pulse.
1 (default) Normal operation and outputs enabled.
TABLE 3K. VC_SEL CONFIGURATION TABLE
Input
Mode of
Operation VC Function
CLKx Input Func-
tion
LF0, LF1, ISET
Function Output FrequencyVC_SEL
0
(default)
Frequency multi-
plier: the refer-
ence clock signal
is jitter attenuated
and frequency-
multiplied
VC input has no function Enabled, the device
locks to CLK0 or
CLK1
Enabled f
OUT
= ((f
REF
/ P)*MV*MF)/N
f
XTAL
= 30.72MHz
The PLL locks to the selected
CLKx input
1
VCXO: the output
frequency is a
function of an
input voltage. The
device can be
used as a inte-
grated oscillator
in an external
PLL
VC controls the VCXO
frequency directly
f
VCXO
= 30.72MHz±50ppm
Disabled Disabled f
OUT
= (30.72MHz ± 50ppm)*MF/N
f
OUT
is pulled by the control voltage
on the VC
pin
Fast Lock Mode
(High VCXO-PLL Bandwidth)
Nominal VCXO-PLL Bandwidth
VCXO-PLL LockedVCXO-PLL Acquires Lock
t
LOCK
LOCK
FLM
0V
V
CC
= 3.3V
FIGURE 2. RECOMMENDED START-UP TIMING DIAGRAM
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

813076CYILFT

Mfr. #:
Buy 813076CYILFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner VCXO FEMTOCLOCK JITTER ATTENUATION
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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