FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
16 REVISION B 7/29/16
SCHEMATIC LAYOUT
Figure 8 shows an example of the ICS813076I application schematic.
In this example, the device is operated at V
CC
= V
CCO
= 3.3V. The
decoupling capacitors should be located as close as possible to
the power pin. The input is driven by a 3.3V LVPECL driver. An
VCC
(U1, 51)
VC
nQB0
R39
4.75K
Set Logic
Input to
'0'
R13
125
nSTOP
NB1
Rs
0.64k
R3
820k
P
(U1, 54)
VCC
(U1, 46)
Cp
0.01uF
LVPECL Driv er
XTAL_IN
Rs
0.64k
C30
0.1u
R13
125
VCCO
Logic Control Input Examples
QA0
TL1
Zo = 50 Ohm
C23
0.01u
Zo = 50
VCCO
R4
82.5
CLK1
Cs
10uF
VC_SEL
C32
0.1u
NB0
nQA0
nMR
Zo = 50 Ohm
Zo = 50
nSTOP
VCC
R2
133
VCCO
RD1
Not Install
(U1, 7)(U1, 30)
MV
C22
SPARE
LF1
C3
220pF
3-pole loop filter example - (optional)
X1
30.72MHz, CL=10pF
LF1
LF0
NC1
R7
50
R1
133
R12
84
nCLK1
VCC
3.3V
VCC
TL2
Zo = 50 Ohm
R4
82.5
QB2
VCC
C40
0.1u
+
-
R3
82.5
nQB2
J30
Zo = 50 Ohm
(U1, 61)
LVPECL Termination
QB2
RD2
1K
Optional
LVPECL
Y-Termination
3.3V
Zo = 50
MF
QB0
nBYPASS
R19
TBD k
C31
0.1u
LF0
C36
0.1u
FLM
R3
82.5
TL2
Zo = 50 Ohm
R11
125
To Logic
Input
pins
(U1, 15)
Set Logic
Input to
'1'
nCLK0
R6
50
R14
84
VCC
NA0
CLK0
VCC
RU1
1K
C21
SPARE
C24
10u
+
-
(U1, 33)
R12
84
R11
125
ISET
(U1, 6)
NA1
R1
133
(U1, 37)
LOCK
QA0
V CCO=3. 3V
NC0
XTAL_OUT
LVPECL Termination
R8
50
C33
0.1u
U1
ICS813076I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
39
38
37
36
35
34
33
32
31
30
29
28
27
52
51
50
49
48
47
46
45
44
43
42
41
40
53
54
55
56
57
58
59
60
61
62
63
64
LF1
LF0
ISET
VC
FLM
VCC
VCC
CLK1
nCLK1
nMR
CLK0
nCLK0
VEE
LOCK
VCCO
NA1
NA0
NB1
NB0
NC1
NC0
P
nBYPASS
nSTOP
REF_SEL
nc
nQA4
QA4
VCC
VEE
nQB0
QB0
VCCO
nQB1
QB1
VCCO
nQB2
QB2
VCCA
nQC0
VCCO
QA0
nQA0
nQA1
QA1
VCCO
nQA2
QA2
VEE
nQA3
QA3
VCCO
QC0
VCCO
VEE
nc
nc
MF
MV
VC_SEL
VCC
XTAL_OUT
XTAL_IN
VEE
LF1
Cs
10uF
R2
133
nQB2
RU2
Not Install
VCC=3.3V
C38
0.1u
TL1
Zo = 50 Ohm
R37 10
(U1, 40)
+
-
LD1
C35
0.1u
R14
84
Zo = 50
nQB0
C40
0.1u
To Logic
Input
pins
C39
0.1u
LVPECL Driv er
nQA0
QB0
VCC
REF_SEL
Cp
0.01uF
VCCA
C37
0.1u
2-pole loop filter with Mid LBW Setting
optional 3-pole fi lter can also be used for additional spur reduction.
It is recommended that the loop fi lter components be laid out for
the 3-pole option. This will also allow the 2-pole fi lter to be used.
FIGURE 8. ICS813076I APPLICATION SCHEMATIC
REVISION B 7/29/16
813076 DATA SHEET
17 FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS813076I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS813076I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE
= 3.465V * 250mA = 866.25mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 9 * 30mW = 270mW
Total Power
_MAX
(3.465V, with all outputs switching) = 866.25mW + 270mW = 1136.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming no air fl ow
and a multi-layer board, the appropriate value is 31.8°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.136W * 31.8°C/W = 121.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ
JA
FOR 64 LEAD TQFP, E-PAD FORCED CONVECTION
θ
JA
by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 31.8°C/W 25.8°C/W 24.2°C/W
REVISION B 7/29/16
813076 DATA SHEET
18 FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 9.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CCO
– 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CCO_MAX
V
OH_MAX
)
= 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.7V
(V
CCO_MAX
V
OL_MAX
)
= 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
– 2V))/R
L
] * (V
CCO_MAX
– V
OH_MAX
) = [(2V – (V
CCO
_MAX
- V
OH_MAX
))
/R
L
] * (V
CCO_MAX
– V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
– 2V))/R
L
] * (V
CCO_MAX
– V
OL_MAX
) = [(2V - (V
CCO
_MAX
V
OL_MAX
))
/R
L
] * (V
CCO_MAX
– V
OL_MAX
) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 9. LVPECL DRIVER CIRCUIT AND TERMINATION
V
OUT
V
CCO
V
CCO
-
2V
Q1
RL
50Ω

813076CYILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner VCXO FEMTOCLOCK JITTER ATTENUATION
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet