REVISION B 7/29/16
813076 DATA SHEET
13 FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
FIGURE 5C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 5B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both V
SWING and VOH must meet the VPP and
V
CMR input requirements. Figures 5A to 5F show interface examples
for the HiPerClockS CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples only.
FIGURE 5A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
HIPERCLOCKS LVHSTL DRIVER
Please consult with the vendor of the driver component to confi rm
the driver termination requirements. For example in Figure 5A, the
input termination applies for IDT HiPerClockS open emitter LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 5E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiver
CLK
nCLK
3.3V
FIGURE 5F. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
14 REVISION B 7/29/16
INPUTS:
CLK/nCLK INPUTS
For applications not requiring the use of the differential input, both
CLK and nCLK can be left fl oating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUTS
All unused LVPECL outputs can be left fl oating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left fl oating or terminated.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate
ECL/LVPECL compatible outputs. Therefore, terminating resistors
(DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50Ω transmission
FIGURE 6B. LVPECL OUTPUT TERMINATION
FIGURE 6A. LVPECL OUTPUT TERMINATION
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 6A
and 6B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it would
be recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component process
variations.
REVISION B 7/29/16
813076 DATA SHEET
15 FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
FIGURE 7. ASSEMBLY FOR EXPOSED PAD T HERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on
the package, as shown in Figure 7. The solderable area on the PCB,
as defi ned by the solder mask, should be at least the same size/
shape as the exposed pad/slug area on the package to maximize
the thermal/electrical performance. Suffi cient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern
must be connected to ground through these vias. The vias act as
“heat pipes”. The number of vias (i.e. “heat pipes”) are application
specifi c and dependent upon the package power dissipation as well
as electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern.
It is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This
is desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadfame Base Package, Amkor Technology.
GROUND PLANE
LAND PATTERN
SOLDER
THERMAL VIA
EXPOSED HEAT SLUG
(GROUND PAD)
PIN
PIN PAD
SOLDER
PIN
PIN PAD
SOLDER

813076CYILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner VCXO FEMTOCLOCK JITTER ATTENUATION
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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