MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I
2
C,
12-Bit ADCs in Ultra-Small Packages
13
Maxim Integrated
Slave Address
A bus master initiates communication with a slave device
by issuing a START condition followed by a slave
address. When idle, the MAX11612–MAX11617 continu-
ously wait for a START condition followed by their slave
address. When the MAX11612–MAX11617 recognize
their slave address, they are ready to accept or send
data. See the
Ordering Information
for the factory pro-
grammed slave address of the selected device. The
least significant bit (LSB) of the address byte (R/W)
determines whether the master is writing to or reading
from the MAX11612–MAX11617 (R/W = 0 selects a write
condition, R/W = 1 selects a read condition). After
receiving the address, the MAX11612–MAX11617
(slave) issues an acknowledge by pulling SDA low for
one clock cycle.
Bus Timing
At power-up, the MAX11612–MAX11617 bus timing is
set for fast-mode (F/S mode), which allows conversion
rates up to 22.2ksps. The MAX11612–MAX11617 must
operate in high-speed mode (HS mode) to achieve con-
version rates up to 94.4ksps. Figure 1 shows the bus tim-
ing for the MAX11612–MAX11617’s 2-wire interface.
HS Mode
At power-up, the MAX11612–MAX11617 bus timing is
set for F/S mode. The bus master selects HS mode by
addressing all devices on the bus with the HS-mode
master code 0000 1XXX (X = don’t care). After success-
fully receiving the HS-mode master code, the
MAX11612–MAX11617 issue a not-acknowledge, allow-
ing SDA to be pulled high for one clock cycle (Figure 8).
After the not-acknowledge, the MAX11612–MAX11617
are in HS mode. The bus master must then send a
repeated START followed by a slave address to initiate
HS mode communication. If the master generates a
STOP condition, the MAX11612–MAX11617 return to
F/S mode.
