MAX11612EUA+ Datasheet MAX11617EEE+T, MAX11617EEE+, MAX11616EEE+ | P16-P18

MAX11612–MAX11617

Low-Power, 4-/8-/12-Channel, I

12-Bit ADCs in Ultra-Small Packages

Maxim Integrated

Data Byte (Read Cycle)

A read cycle must be initiated to obtain conversion

results. Read cycles begin with the bus master issuing

a START condition followed by seven address bits and

a read bit (R/W = 1). If the address byte is successfully

received, the MAX11612–MAX11617 (slave) issues an

acknowledge. The master then reads from the slave.

The result is transmitted in two bytes; first four bits of

the first byte are high, then MSB through LSB are con-

secutively clocked out. After the master has received

the byte(s), it can issue an acknowledge if it wants to

continue reading or a not-acknowledge if it no longer

wishes to read. If the MAX11612–MAX11617 receive a

not-acknowledge, they release SDA, allowing the master

to generate a STOP or a repeated START condition. See

the

Clock Modes

and

Scan Mode

sections for detailed

information on how data is obtained and converted.

Clock Modes

The clock mode determines the conversion clock and

the data acquisition and conversion time. The clock

mode also affects the scan mode. The state of the set-

up byte’s CLK bit determines the clock mode (Table 1).

At power-up, the MAX11612–MAX11617 are defaulted

to internal clock mode (CLK = 0).

Internal Clock

When configured for internal clock mode (CLK = 0), the

MAX11612–MAX11617 use their internal oscillator as the

conversion clock. In internal clock mode, the MAX11612–

MAX11617 begin tracking the analog input after a valid

address on the eighth rising edge of the clock. On the

falling edge of the ninth clock, the analog signal is acquired

and the conversion begins. While converting the analog

input signal, the MAX11612–MAX11617 holds SCL low

(clock stretching). After the conversion completes, the

results are stored in internal memory. If the scan mode is set

for multiple conversions, they all happen in succession with

each additional result stored in memory. The MAX11612/

MAX11613 contain four 12-bit blocks of memory, the

MAX11614/MAX11615 contain eight 12-bit blocks of memo-

ry, and the MAX11616/MAX11617 contain twelve 12-bit

blocks of memory. Once all conversions are complete, the

MAX11612–MAX11617 release SCL, allowing it to be pulled

high. The master can now clock the results out of the mem-

ory in the same order the scan conversion has been done

at a clock rate of up to 1.7MHz. SCL is stretched for a maxi-

mum of 8.3µs per channel (see Figure 10).

The device memory contains all of the conversion

results when the MAX11612–MAX11617 release SCL.

CS3

CS2

CS1 CS0 AIN0 AIN1 AIN2 AIN3

AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10

AIN11

0000+ -

0001-+

0010 +-

0011 -+

0100 +-

0101 -+

0110 +-

0111 -+

1000 +-

1001 -+

1010 +-

1011 -+

1100 RESERVED

1101 RESERVED

1110 RESERVED

1111 RESERVED

For the MAX11612/MAX11613, CS3 and CS2 are internally set to 0. For the MAX11614/MAX11615, CS3 is internally set to 0.

When SEL1 = 1, a differential read between AIN2 and AIN3/REF (MAX11612/MAX11613) or AIN10 and AIN11/REF

(MAX11616/MAX11617) returns the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of 1011

returns the negative difference between AIN10 and GND. This does not apply to the MAX11614/MAX11615 as each provides separate

pins for AIN7 and REF. In differential scanning, the address increments by 2 until the limit set by CS3–CS1 has been reached.

Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)

MAX11612–MAX11617

Low-Power, 4-/8-/12-Channel, I

12-Bit ADCs in Ultra-Small Packages

Maxim Integrated

The converted results are read back in a first-in-first-out

(FIFO) sequence. If AIN_/REF is set to be a reference

input or output (SEL1 = 1, Table 6), AIN_/REF is exclud-

ed from a multichannel scan. This does not apply to the

MAX11614/MAX11615 as each provides separate pins

for AIN7 and REF. The memory contents can be read

continuously. If reading continues past the result stored

in memory, the pointer wraps around and point to the

first result. Note that only the current conversion results

is read from memory. The device must be addressed

with a read command to obtain new conversion results.

The internal clock mode’s clock stretching quiets the

SCL bus signal reducing the system noise during

conversion. Using the internal clock also frees the bus

master (typically a microcontroller) from the burden of

running the conversion clock, allowing it to perform

other tasks that do not need to use the bus.

External Clock

When configured for external clock mode (CLK = 1),

the MAX11612–MAX11617 use the SCL as the conver-

sion clock. In external clock mode, the MAX11612–

MAX11617 begin tracking the analog input on the ninth

rising clock edge of a valid slave address byte. Two

SCL clock cycles later, the analog signal is acquired

and the conversion begins. Unlike internal clock mode,

B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK

SLAVE ADDRESS A

711

CLOCK STRETCH

NUMBER OF BITS

P or Sr

RESULT 8 LSBs

RESULT 4 MSBs A

A. SINGLE CONVERSION WITH INTERNAL CLOCK

SLAVE ADDRESS

711

CLOCK STRETCH

NUMBER OF BITS

P or Sr

RESULT 1 ( 4MSBs) A

RESULT 1 (8 LSBs) A

RESULT N (8LSBs)A

RESULT N (4MSBs)

SLAVE TO MASTER

MASTER TO SLAVE

CLOCK STRETCH

ACQ1

CONV2

ACQ2

CONVN

ACQN

CONV

ACQ

CONV1

Figure 10. Internal Clock Mode Read Cycles

SLAVE ADDRESS

CONV1

ACQ1

ACQ2

CONVN

ACQN

CONV

ACQ

NUMBER OF BITS

711

P OR Sr

B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK

SLAVE ADDRESS P OR SrRESULT (8 LSBs)

RESULT (4 MSBs)

A. SINGLE CONVERSION WITH EXTERNAL CLOCK

SLAVE TO MASTER

MASTER TO SLAVE

RESULT 1 (4 MSBs) RESULT 2 (8 LSBs) RESULT N (8 LSBs)

RESULT N (4 MSBs)

Figure 11. External Clock Mode Read Cycle

MAX11612–MAX11617

Low-Power, 4-/8-/12-Channel, I

12-Bit ADCs in Ultra-Small Packages

Maxim Integrated

converted data is available immediately after the first

four empty high bits. The device continuously converts

input channels dictated by the scan mode until given a

not acknowledge. There is no need to readdress the

device with a read command to obtain new conversion

results (see Figure 11).

The conversion must complete in 1ms, or droop on the

track-and-hold capacitor degrades conversion results.

Use internal clock mode if the SCL clock period

exceeds 60µs.

The MAX11612–MAX11617 must operate in external

clock mode for conversion rates from 40ksps to

94.4ksps. Below 40ksps, internal clock mode is recom-

mended due to much smaller power consumption.

Scan Mode

SCAN0 and SCAN1 of the configuration byte set the

scan mode configuration. Table 5 shows the scanning

configurations. If AIN_/REF is set to be a reference input

or output (SEL1 = 1, Table 6), AIN_/REF is excluded from

a multichannel scan. The scanned results are written to

memory in the same order as the conversion. Read the

results from memory in the order they were converted.

Each result needs a 2-byte transmission; the first byte

begins with four empty bits, during which SDA is left

high. Each byte has to be acknowledged by the master

or the memory transmission is terminated. It is not possi-

ble to read the memory independently of conversion.

Applications Information

Power-On Reset

The configuration and setup registers (Tables 1 and 2)

default to a single-ended, unipolar, single-channel con-

version on AIN0 using the internal clock with V

as the

reference and AIN_/REF configured as an analog input.

The memory contents are unknown after power-up.

Automatic Shutdown

Automatic shutdown occurs between conversions when

the MAX11612–MAX11617 are idle. All analog circuits

participate in automatic shutdown except the internal

reference due to its prohibitively long wake-up time.

When operating in external clock mode, a STOP, not-

acknowledge, or repeated START condition must be

issued to place the devices in idle mode and benefit

from automatic shutdown. A STOP condition is not nec-

essary in internal clock mode to benefit from automatic

shutdown because power-down occurs once all con-

version results are written to memory (Figure 10). When

using an external reference or V

as a reference, all

analog circuitry is inactive in shutdown and supply cur-

rent is less than 0.5µA. The digital conversion results

obtained in internal clock mode are maintained in memo-

ry during shutdown and are available for access through

the serial interface at any time prior to a STOP or a

repeated START condition.

SCAN1 SCAN0

SCANNING CONFIGURATION

Scans up from AIN0 to the input selected by CS3–CS0. When CS3–CS0 exceeds 1011, the scanning

stops at AIN11. When AIN_/REF is set to be a REF input/output, scanning stops at AIN2 or AIN10.

0 1 *Converts the input selected by CS3–CS0 eight times (see Tables 3 and 4).

MAX11612/MAX11613: Scans upper half of channels.

Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0, AIN1,

and AIN2, the only scan that takes place is AIN2 (MAX11612/MAX11613). When AIN/REF is set to be a

REF input/output, scanning stops at AIN2.

MAX11614/MAX11615: Scans upper quartile of channels.

Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only

scan that takes place is AIN6 (MAX11614/MAX11615).

MAX11616/MAX11617: Scans upper half of channels.

Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only

scan that takes place is AIN6 (MAX11616/MAX11617). When AIN/REF is set to be a REF input/output,

scanning stops at selected channel or AIN10.

1 1 *Converts channel selected by CS3–CS0.

When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs

perpetually until not-acknowledge occurs.

Table 5. Scanning Configuration

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

MAX11612EUA+

Mfr. #:

Buy MAX11612EUA+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 12-Bit 4Ch 94.4sps 5.5V Precision ADC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX11612EUA+

MAX11612EUA+

Products related to this Datasheet