MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I
2
C,
12-Bit ADCs in Ultra-Small Packages
19
Maxim Integrated
When idle, the MAX11612–MAX11617 continuously wait
for a START condition followed by their slave address
(see the
Slave Address
section). Upon reading a valid
address byte, the MAX11612–MAX11617 power up.
The internal reference requires 10ms to wake up, so
when using the internal reference it should be powered
up 10ms prior to conversion or powered continuously.
Wake-up is invisible when using an external reference
or V
DD
as the reference.
Automatic shutdown results in dramatic power savings,
particularly at slow conversion rates and with internal
clock. For example, at a conversion rate of 10ksps, the
average supply current for the MAX11613 is 60µA (typ)
and drops to 6µA (typ) at 1ksps. At 0.1ksps the average
supply current is just 1µA, or a minuscule 3µW of power
consumption. See Average Supply Current vs. Conversion
Rate in the
Typical Operating Characteristics
section).
Reference Voltage
SEL[2:0] of the setup byte (Table 1) control the reference
and the AIN_/REF configuration (Table 6). When AIN_/REF
is configured to be a reference input or reference output
(SEL1 = 1), differential conversions on AIN_/REF appear
as if AIN_/REF is connected to GND (see note 2 of Table
4). Single-ended conversion in scan mode AIN_/REF is
ignored by the internal limiter, which sets the highest avail-
able channel at AIN2 or AIN10.
Internal Reference
The internal reference is 4.096V for the MAX11612/
MAX11614/MAX11616 and 2.048V for the MAX11613/
MAX11615/MAX11617. SEL1 of the setup byte controls
whether AIN_/REF is used for an analog input or a refer-
ence (Table 6). When AIN_/REF is configured to be an
internal reference output (SEL[2:1] = 11), decouple
AIN_/REF to GND with a 0.1µF capacitor and a 2kΩ
series resistor (see the
Typical Operating Circuit
). Once
powered up, the reference always remains on until recon-
figured. The internal reference requires 10ms to wake up
and is accessed using SEL0 (Table 6). When in shutdown,
the internal reference output is in a high-impedance state.
The reference should not be used to supply current for
external circuitry. The internal reference does not require an
external bypass capacitor and works best when left uncon-
nected (SEL1 = 0).
External Reference
The external reference can range from 1V to V
DD
. For
maximum conversion accuracy, the reference must be
able to deliver up to 40µA and have an output imped-
ance of 500kΩ or less. If the reference has a higher out-
put impedance or is noisy, bypass it to GND as close to
AIN_/REF as possible with a 0.1µF capacitor.
SEL2 SEL1 SEL0
REFERENCE
VOLTAGE
AIN_/REF
(MAX11612/
MAX11613/
MAX11616/
MAX11617)
REF
(MAX11614/
MAX11615)
INTERNAL
REFERENCE
STATE
00X V
DD
Analog input Not connected Always off
01X
External reference
Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected Always off
1 0 1 Internal reference Analog input Not connected Always on
1 1 0 Internal reference Reference output Reference output Always off
1 1 1 Internal reference Reference output Reference output Always on
Table 6. Reference Voltage, AIN_/REF, and REF Format
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
123
0
FS
FS - 3/2 LSB
FS = V
REF
ZS = GND
INPUT VOLTAGE (LSB)
MAX11612–
MAX11617
1 LSB =
V
REF
4096
Figure 12. Unipolar Transfer Function
X = Don’t care.
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I
2
C,
12-Bit ADCs in Ultra-Small Packages
20
Maxim Integrated
Transfer Functions
Output data coding for the MAX11612–MAX11617 is
binary in unipolar mode and two’s complement in bipo-
lar mode with 1 LSB = (V
REF
/2N) where N is the number
of bits (12). Code transitions occur halfway between
successive-integer LSB values. Figures 12 and 13
show the input/output (I/O) transfer functions for unipo-
lar and bipolar operations, respectively.
Layout, Grounding, and Bypassing
Only use PC boards. Wire-wrap configurations are not
recommended since the layout should ensure proper
separation of analog and digital traces. Do not run ana-
log and digital lines parallel to each other, and do not
layout digital signal paths underneath the ADC pack-
age. Use separate analog and digital PCB ground sec-
tions with only one star point (Figure 14) connecting the
two ground systems (analog and digital). For lowest
noise operation, ensure the ground return to the star
ground’s power supply is low impedance and as short
as possible. Route digital signals far away from sensi-
tive analog and reference inputs.
High-frequency noise in the power supply (V
DD
) could
influence the proper operation of the ADC’s fast com-
parator. Bypass V
DD
to the star ground with a network of
two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX11612–MAX11617 power-
supply pin. Minimize capacitor lead length for best sup-
ply noise rejection, and add an attenuation resistor (5Ω)
in series with the power supply if it is extremely noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once offset
and gain errors have been nullified. The MAX11612–
MAX11617’s INL is measured using the endpoint.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (t
AJ
) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (t
AD
) is the time between the falling
edge of the sampling clock and the instant when an
actual sample is taken.
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
- FS
0
INPUT VOLTAGE (LSB)
OUTPUT CODE
ZS = 0
+FS - 1 LSB
*V
COM
V
REF
/2 *V
IN
= (AIN+) - (AIN-)
FS
=
V
REF
2
-FS =
-V
REF
2
MAX11612–
MAX11617
1 LSB =
V
REF
4096
Figure 13. Bipolar Transfer Function
GND
V
LOGIC
= 3V/5V3V OR 5V
SUPPLIES
DGND3V/5VGND
*OPTIONAL
4.7μF
R* = 5Ω
0.1μF
V
DD
DIGITAL
CIRCUITRY
MAX11612–
MAX11617
Figure 14. Power-Supply Grounding Connection
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I
2
C,
12-Bit ADCs in Ultra-Small Packages
21
Maxim Integrated
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana-
log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N Bits):
SNR
MAX[dB]
= 6.02
dB
N + 1.76
dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
where V
1
is the fundamental amplitude, and V
2
through
V
5
are the amplitudes of the 2nd- through 5th-order har-
monics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
THD
VVVV
V
log
+++
20
2
2
3
2
4
2
5
2
1
SINAD dB
SignalRMS
NoiseRMS THDRMS
( ) log
+
20
Chip Information
PROCESS: BiCMOS
PART
INPUT
CHANNELS
INTERNAL
REFERENCE
(V)
SUPPLY
VOLTAGE
(V)
INL
(LSB)
MAX11612
4 4.096
4.5 to 5.5
±1
MAX11613
4 2.048
2.7 to 3.6
±1
MAX11614
8 4.096
4.5 to 5.5
±1
MAX11615
8 2.048
2.7 to 3.6
±1
MAX11616
12 4.096
4.5 to 5.5
±1
MAX11617
12 2.048
2.7 to 3.6
±1
Selector Guide

MAX11612EUA+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 4Ch 94.4sps 5.5V Precision ADC
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New from this manufacturer.
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