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MAX11612EUA+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I
2
C,
12-Bit ADCs in Ultra-Small Packages
4
Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), V
DD
= 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), V
REF
= 2.048V
(MAX11613/MAX11615/MAX11617), V
REF
= 4.096V (MAX11612/MAX11614/MAX11616), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C, see Tables 1–5 for programming notation.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
POWER REQUIREMENTS
MAX11613/MAX11615/MAX11617 2.7 3.6
Supply Voltage V
DD
MAX11612/MAX11614/MAX11616 4.5 5.5
V
Internal reference
900 1150
f
SAMPLE
= 94.4ksps
external clock
External reference
670
900
Internal reference
530
f
SAMPLE
= 40ksps
internal clock
External reference
230
Internal reference
380
f
SAMPLE
= 10ksps
internal clock
External reference 60
Internal reference
330
f
SAMPLE
=1ksps
internal clock
External reference 6
Supply Current I
DD
Shutdown (internal REF off) 0.5 10
µA
Power-Supply Rejection Ratio PSRR Full-scale input (Note 10)
±0.5 ±2.0
TIMING CHARACTERISTICS (Figure 1)
(V
DD
= 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), V
DD
= 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), V
REF
= 2.048V
(MAX11613/MAX11615/MAX11617), V
REF
= 4.096V (MAX11612/MAX11614/MAX11616), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C, see Tables 1–5 for programming notation.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency f
SCL
400 kHz
Bus Free Time Between a STOP (P)
and a START (S) Condition
t
BUF
1.3 µs
Hold Time for START (S) Condition
t
HD
,
STA
0.6 µs
Low Period of the SCL Clock t
LOW
1.3 µs
High Period of the SCL Clock t
HIGH
0.6 µs
Setup Time for a Repeated START
Condition (Sr)
t
SU
,
STA
0.6 µs
Data Hold Time (Note 11)
t
HD
,
DAT
0 900 ns
Data Setup Time
t
SU
,
DAT
100
ns
Rise Time of Both SDA and SCL
Signals, Receiving
t
R
Measured from 0.3V
DD
- 0.7V
DD
20 + 0.1C
B
300 ns
Fall Time of SDA Transmitting t
F
Measured from 0.3V
DD
- 0.7V
DD
(Note 12)
20 + 0.1C
B
300 ns
Setup Time for STOP (P) Condition
t
SU
,
STO
0.6 µs
Capacitive Load for Each Bus Line
C
B
400 pF
Pulse Width of Spike Suppressed
t
SP
50 ns
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I
2
C,
12-Bit ADCs in Ultra-Small Packages
5
Maxim Integrated
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C
B
= 400pF, Note 13)
Serial-Clock Frequency
f
SCLH
(Note 14) 1.7
MHz
Hold Time, Repeated START
Condition (Sr)
t
HD
,
STA
160
ns
Low Period of the SCL Clock t
LOW
320
ns
High Period of the SCL Clock t
HIGH
120
ns
Setup Time for a Repeated START
Condition (Sr)
t
SU
,
STA
160
ns
Data Hold Time
t
HD
,
DAT
(Note 11) 0 150 ns
Data Setup Time
t
SU
,
DAT
10 ns
Rise Time of SCL Signal
(Current Source Enabled)
t
RCL
20 80 ns
Rise Time of SCL Signal After
Acknowledge Bit
t
RCL1
Measured from 0.3V
DD
- 0.7V
DD
20 160 ns
Fall Time of SCL Signal t
FCL
Measured from 0.3V
DD
- 0.7V
DD
20 80 ns
Rise Time of SDA Signal t
RDA
Measured from 0.3V
DD
- 0.7V
DD
20 160 ns
Fall Time of SDA Signal t
FDA
Measured from 0.3V
DD
- 0.7V
DD
(Note 12) 20 160 ns
Setup Time for STOP (P) Condition
t
SU
,
STO
160
ns
Capacitive Load for Each Bus Line
C
B
400 pF
Pulse Width of Spike Suppressed
t
SP
(Notes 11 and 14) 0 10 ns
TIMING CHARACTERISTICS (Figure 1) (continued)
(V
DD
= 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), V
DD
= 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), V
REF
= 2.048V
(MAX11613/MAX11615/MAX11617), V
REF
= 4.096V (MAX11612/MAX11614/MAX11616), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C, see Tables 1–5 for programming notation.) (Note 1)
Note 1: All WLP devices are 100% production tested at T
A
= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2: For DC accuracy, the MAX11612/MAX11614/MAX11616 are tested at V
DD
= 5V and the
MAX11613/MAX11615/MAX11617are tested at V
DD
= 3V. All devices are configured for unipolar, single-ended inputs.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4: Offset nulled.
Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V
DD
.
Note 8: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩ series resistor (see the
Typical Operating Circuit
).
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µV
P-P
.
Note 10: Measured as for the MAX11613/MAX11615/MAX11617:
VVVV
V
VV
FS FS
REF
N
(. ) (. )
(. . )
36 27
21
36 27
−
−
−
[]
×
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
Typical Operating Characteristics
(V
DD
= 3.3V (MAX11613/MAX11615/MAX11617), V
DD
= 5V (MAX11612/MAX11614/MAX11616), f
SCL
= 1.7MHz, (50% duty cycle),
f
SAMPLE
= 94.4ksps, single-ended, unipolar, T
A
= +25°C, unless otherwise noted.)
-0.5
-0.2
-0.4
-0.3
0.2
0.1
0.1
0
0.3
0.5
0 4000
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
MAX11612 toc01
DIGITAL OUTPUT CODE
DNL (LSB)
1000 1500500
2000 2500
3000 3500
0.4
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
MAX11612 toc02
DIGITAL OUTPUT CODE
INL (LSB)
0 4000
1000 1500500
2000 2500
3000 3500
-180
-160
-140
-120
-100
-80
-60
0 10k 20k 30k 40k 50k
FFT PLOT
MAX11612 toc03
FREQUENCY (Hz)
AMPLITUDE (dBc)
f
SAMPLE
= 94.4ksps
f
IN
= 10kHz
300
400
350
500
450
600
550
650
750
700
800
-40 -10 5-25 20 35 50 65 80
SUPPLY CURRENT
vs. TEMPERATURE
MAX11612 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
INTERNAL REFERENCE MAX11617/MAX11615/
MAX11613
INTERNAL REFERENCE MAX11616/MAX11614/
MAX11612
EXTERNAL REFERENCE MAX11616/MAX11614/
MAX11612
EXTERNAL REFERENCE MAX11617/MAX11615/
MAX11613
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
0
0.2
0.1
0.4
0.3
0.5
0.6
2.7 5.2
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX11612 toc05
SUPPLY VOLTAGE (V)
I
DD
(μA)
3.73.2 4.2 4.7
SDA = SCL = V
DD
0
0.10
0.05
0.20
0.15
0.30
0.25
0.35
0.45
0.40
0.50
-40 -10 5
-25
20 35 50 65 80
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX11612 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
MAX11616/MAX11614/MAX11612
MAX11617/MAX11615/MAX11613
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I
2
C,
12-Bit ADCs in Ultra-Small Packages
6
Maxim Integrated
and for the MAX11612/MAX11614/MAX11616, where N is the number of bits:
Note 11: A master device must provide a data hold time for SDA (referred to V
IL
of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12: The minimum value is specified at T
A
= +25°C.
Note 13: C
B
= total capacitance of one bus line in pF.
Note 14: f
SCL
must meet the minimum clock low time plus the rise/fall times.
VVVV
V
VV
FS FS
REF
N
(. ) (. )
(. . )
55 45
21
55 45
−
−
−
[]
×
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
TIMING CHARACTERISTICS (Figure 1) (continued)
(V
DD
= 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), V
DD
= 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), V
REF
= 2.048V
(MAX11613/MAX11615/MAX11617), V
REF
= 4.096V (MAX11612/MAX11614/MAX11616), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C, see Tables 1–5 for programming notation.) (Note 1)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

MAX11612EUA+

Mfr. #:
Buy MAX11612EUA+
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 4Ch 94.4sps 5.5V Precision ADC
Lifecycle:
New from this manufacturer.
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