LTC3723EGN-2#TRPBF Datasheet LTC3723EGN-2#TRPBF, LTC3723EGN-1#TRPBF, LTC3723EGN-1#PBF | P10-P12

LTC3723-1/LTC3723-2

372312f

–

TURN-ON

OUTPUT

2.5V

–

10µA

REF

DPRG

372312 F01

200kOPTIONAL

Please refer to the detailed Block Diagrams for this discus-

sion. The LTC3723-1 and LTC3723-2 are synchronous

PWM push-pull controllers. The LTC3723-1 operates with

peak pulse-by-pulse current mode control while the

LTC3723-2 offers voltage mode control operation. They

are best suited for moderate to high power isolated power

systems where small size and high efficiency are required.

The push-pull topology delivers excellent transformer

utilization and requires only two low side power MOSFET

switches. Both controllers generate 180° out of phase

0% to < 50% duty cycle drive signals on DRVA and DRVB.

The external MOSFETs are driven directly by these power-

ful on-chip drivers. The external MOSFETs typically con-

trol opposite primary windings of a centertapped power

transformer. The centertap primary winding is connected

to the input DC feed. The secondary of the transformer can

be configured in different synchronous or nonsynchronous

configurations depending on the application needs.

The duty ratio is controlled by the voltage on COMP. A

switching cycle commences with the falling edge of the

internal oscillator clock pulse. The LTC3723-1 attenuates

the voltage on COMP and compares it to the current sense

signal to terminate the switching cycle. The LTC3723-2

compares the voltage on COMP to a timing ramp to

terminate the cycle. The LTC3723-2’s C

waveform can be

used for this purpose or separate R-C components can be

connected to RAMP to generate the timing ramp. If the

voltage on CS exceeds 300mV, the present cycle is termi-

nated. If the voltage on CS exceeds 600mV, all switching

stops and a soft-start sequence is initiated.

The LTC3723-1 / LTC3723-2 also provide drive signals for

secondary side synchronous rectifier MOSFETs. Synchro-

nous rectification improves converter efficiency, espe-

cially as the output voltages drop. Independent turn-off

control of the synchronous rectifiers is provided via SPRG

in order to optimize the benefit of the synchronous recti-

fiers. A resistor from SPRG to GND sets the desired turn

off delay.

A host of other features including an error amplifier,

system UVLO programming, adjustable leading edge blank-

ing, slope compensation and programmable dead-time

provide flexibility for a variety of applications.

OPERATIO

Programming Driver Dead-Time

The LTC3723-1/LTC3723-2 controllers include a feature

to program the minimum time between the output signals

on DRVA and DRVB commonly referred to as the driver

dead-time. This function will come into play if the control-

ler is commanded for maximum duty cycle. The dead-time

is set with an external resistor connected between DPRG

and V

REF

(see Figure 1). The nominal regulated voltage on

DPRG is 2V. The external resistor programs a current

which flows into DPRG. The dead-time can be adjusted

from 90ns to 300ns with this resistor. The dead-time can

also be modulated based on an external current source

that feeds current into DPRG. Care must be taken to limit

the current fed into DPRG to 350µA or less. An internal

10µA current source sets a maximum deadtime if DPRG is

floated. The internal current source causes the programmed

deadtime to vary non-linearly with increasing values of

RDPRG (see typical performance characteristics). An ex-

ternal 200k resistor connected from DPRG to GND will

compensate for the internal 10µA current source and

linearize the deadtime delay vs RDPRG characteristic.

Powering the LTC3723-1/LTC3723-2

The LTC3723-1/LTC3723-2 utilize an integrated V

shunt

regulator to serve the dual purposes of limiting the voltage

applied to V

as well as signaling that the chip’s bias

voltage is sufficient to begin switching operation (under

voltage lockout). With its typical 10.2V turn-on voltage

and 4.2V UVLO hysteresis, the LTC3723-1/LTC3723-2 is

tolerant of loosely regulated input sources such as an

auxiliary transformer winding. The V

shunt is capable of

sinking up to 40mA of externally applied current. The

UVLO turn-on and turn-off thresholds are derived from an

internally trimmed reference making them extremely ac-

curate. In addition, the LTC3723-1/LTC3723-2 exhibits

Figure 1. Delay Timeout Circuitry

LTC3723-1/LTC3723-2

372312f

very low (145µA typ) start-up current that allows the use

of 1/8W to 1/4W trickle charge start-up resistors.

The trickle charge resistor should be selected as follows:

START(MAX)

= V

IN(MIN)

– 10.7V/250µA

Adding a small safety margin and choosing standard

values yields:

APPLICATION V

RANGE R

START

DC/DC 36V to 72V 100k

Off-Line 85V to 270V

RMS

430k

PFC Preregulator 390V

1.4M

should be bypassed with a 0.1µF to 1µF multilayer

ceramic capacitor to decouple the fast transient currents

demanded by the output drivers and a bulk tantalum or

electrolytic capacitor to hold up the V

supply before the

bootstrap winding, or an auxiliary regulator circuit takes

over.

HOLDUP

= (I

+ I

DRIVE

) • t

DELAY

/3.8V

(minimum UVLO hysteresis)

Regulated bias supplies as low as 7V can be utilized to

provide bias to the LTC3723-1/LTC3723-2. Refer to

Figure 2 for various bias supply configurations.

Figure 2. Bias Configurations

372312 F02

12V ±10%

1.5k

HOLD

1N5226

1µF

BIAS

< V

UVLO

START

1N914

Figure 3. System UVLO Setup

ON OFF

BOTTOM

TOP

UVLO

372312 F03

OPERATIO

UVLO. The amount of DC feed hysteresis provided by this

current is: 10µA • R

TOP

, (Figure 3). The system UVLO

threshold is: 5V • {(R

TOP

+ R

BOTTOM

)/R

BOTTOM

}. If the

voltage applied to UVLO is present and greater than 5V

prior to the V

UVLO circuitry activation, then the internal

UVLO logic will prevent output switching until the follow-

ing three conditions are met: (1) V

UVLO is enabled, (2)

REF

is in regulation and (3) UVLO pin is greater than 5V.

UVLO can also be used to enable and disable the power

converter. An open drain transistor connected to UVLO as

shown in Figure 3 provides this capability.

Programming Undervoltage Lockout

The LTC3723-1/LTC3723-2 provides undervoltage lock-

out (UVLO) control for the input DC voltage feed to the

power converter in addition to the V

UVLO function

described in the preceding section. Input DC feed UVLO is

provided with the UVLO pin. A comparator on UVLO

compares a divided down input DC feed voltage to the 5V

precision reference. When the 5V level is exceeded on

UVLO, the SS pin is released and output switching com-

mences. At the same time a 10µA current is enabled which

flows out of UVLO into the voltage divider connected to

Off-Line Bias Supply Generation

If a regulated bias supply is not available to provide V

voltage to the LTC3723-1/LTC3723-2 and supporting

circuitry, one must be generated. Since the power require-

ment is small, approximately 1W, and the regulation is not

critical, a simple open-loop method is usually the easiest

and lowest cost approach. One method that works well is

to add a winding to the main power transformer, and post

regulate the resultant square wave with an L-C filter (see

Figure 4a). The advantage of this approach is that it

maintains decent regulation as the supply voltage varies,

and it does not require full safety isolation from the input

winding of the transformer. Some manufacturers include

a primary winding for this purpose in their standard

Figure 4a. Auxiliary Winding Bias Supply

372312 F04a

HOLD

1µF

START

15V*

*OPTIONAL

LTC3723-1/LTC3723-2

372312f

OPERATIO

product offerings as well. A different approach is to add a

winding to the output inductor and peak detect and filter

the square wave signal (see Figure 4b). The polarity of this

winding is designed so that the positive voltage square

wave is produced while the output inductor is freewheel-

ing. An advantage of this technique over the previous is

that it does not require a separate filter inductor and since

the voltage is derived from the well-regulated output

voltage, it is also well controlled. One disadvantage is that

this winding will require the same safety isolation that is

required for the main transformer. Another disadvantage

is that a much larger V

filter capacitor is needed, since

it does not generate a voltage as the output is first starting

up, or during short-circuit conditions.

Figure 4b. Output Inductor Bias Supply

372312 F04b

OUT

HOLD

START

1µF

OUT

ISO BARRIER

Programming the LTC3723-1/LTC3723-2 Oscillator

The high accuracy LTC3723-1/LTC3723-2 oscillator cir-

cuit provides flexibility to program the switching fre-

quency and slope compensation required for current

mode control (LTC3723-1). The oscillator circuit pro-

duces a 2.35V peak-to-peak amplitude ramp waveform on

. Typical maximum duty cycles of 49% are possible. The

oscillator is capable of operation up to 1MHz by the

following equation:

= 1/(14.8k • F

OSC

)

Note that this is the frequency seen on C

. The output

drivers switch at 1/2 of this frequency. Also note that

higher switching frequency and added driver dead-time

via DPRG will reduce the maximum duty cycle.

The LTC3723-1/LTC3723-2 can be synchronized to an

external frequency source such as another PWM chip. In

Single-Ended Operation

In addition to push-pull and full-bridge topologies, single-

ended topologies such as the forward and flyback con-

verter can benefit from the many advanced features of the

LTC3723. In Figure 6, the LTC3723 is used with the

LTC4440, 100V high side driver to implement a two-

transistor forward converter. DRVB is used which limits

the converter’s maximum duty cycle to 50% (less pro-

grammable driver dead time).

LTC3723

OSC

< f

EXT

< 1.25 • f

OSC

= f

OSC

/2 f

OSC

≅

68pF

372312 F05

390Ω

BAT54

210µA

2.56V •

EXTERNAL

FREQUENCY

SOURCE

Figure 5. Synchronization from External Source

Figure 6. Two-Transistor Forward Converter (Duty Cycle < 50%)

210µA

2 • 2.56V • C

LTC3723

DRVB

GND

TO SYNCHRONOUS

SECONDARY MOSFET

LTC4440

372312 F06

GND

•

SDRB

≅

–V

Figure 5, the leading edge of an external pulse is used to

terminate the natural clock cycle. If the external frequency

is higher than the oscillator frequency, the internal oscil-

lator will synchronize with the external input frequency.

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LTC3723EGN-2#TRPBF

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Description:

Switching Voltage Regulators Push Pull Pwm Controllers

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