LTC3723-1/LTC3723-2
6
372312f
V
REF
(Pin 1/Pin 1): Output of the 5.0V Reference. V
REF
is
capable of supplying up to 18mA to external circuitry. V
REF
should be decoupled to GND with a 0.47µF ceramic
capacitor.
SDRB (Pin 2/Pin 2): 50mA Driver for Synchronous Recti-
fier associated with DRVB.
SDRA (Pin 3/Pin 3): 50mA Driver for Synchronous Recti-
fier associated with DRVA.
DRVB (Pin 4/Pin 4): High Speed 1.5A Sink, 1A Source
Totem Pole MOSFET Driver. Connect to gate of external
push-pull MOSFET with as short a PCB trace as practical
to preserve drive signal integrity. A low value resistor
connected between DRVA and the MOSFET gate is op-
tional and will improve the gate drive signal quality if the
PCB trace from the driver to the MOSFET cannot be made
short.
V
CC
(Pin 5/Pin 5): Supply Voltage Input to the LTC3723-1/
LTC3723-2 and 10.25V Shunt Regulator. The chip is
enabled after V
CC
has risen high enough to allow the V
CC
shunt regulator to conduct current and the UVLO com-
parator threshold is exceeded. Once the V
CC
shunt regu-
lator has turned on, V
CC
can drop to as low as 6V (typical)
and maintain operation. Bypass V
CC
to GND with a high
quality 1µF or larger ceramic capacitor to supply the
transient currents caused by the high speed switching and
capacitive loads presented by the on chip totem pole
drivers.
DRVA (Pin 6/Pin 6): High Speed 1.5A Sink, 1A Source
Totem Pole MOSFET Driver. Connect to gate of external
push-pull MOSFET with as short a PCB trace as practical
to preserve drive signal integrity. A low value resistor
connected between DRVA and the MOSFET gate is op-
tional and will improve the gate drive signal quality if the
PCB trace from the driver to the MOSFET cannot be made
short.
GND (Pin 7/Pin 7): All circuits in the LTC3723 are refer-
enced to GND. Use of a ground plane is highly recom-
DESCRIPTIO S
U
PI
U
(LTC3723-1/LTC3723-2)
mended. V
IN
and V
REF
bypass capacitors must be termi-
nated with a star configuration as close to GND as practical
for best performance.
C
T
(Pin 8/Pin 8): Timing Capacitor for the Oscillator. Use
a ±5% or better low ESR ceramic capacitor for best
results. C
T
ramp amplitude is 2.35V peak-to-peak
(typical).
DPRG (Pin 9/Pin 12): Programming Input for Push-Pull
Dead-Time. Connect a resistor between DPRG and V
REF
to program the dead-time. The nominal voltage on DPRG
is 2V.
RAMP (N/A/Pin 9): Input to PWM Comparator for
LTC3723-2 Only (Voltage Mode Controller). The voltage
on RAMP is internally level shifted by 650mV.
CS (Pin 10/Pin 10): Input to Pulse-by-Pulse and Overload
Current Limit Comparators, Output of Slope Compensa-
tion Circuitry. The pulse-by-pulse comparator has a nomi-
nal 300mV threshold, while the overload comparator has
a nominal 600mV threshold. An internal switch discharges
CS to GND after every timing period. Slope compensation
current flows out of CS during the PWM period.
An external resistor connected from CS to the external
current sense resistor programs the amount of slope
compensation.
COMP (Pin 11/Pin 11): Error Amplifier Output, Inverting
Input to Phase Modulator.
R
LEB
(Pin 12/N/A): Timing Resistor for Leading Edge
Blanking. Use a 10k to 100k resistor connected between
R
LEB
and GND to program from 40ns to 310ns of leading
edge blanking of the current sense signal on CS for the
LTC3723-1. A ±1% tolerance resistor is recommended.
The LTC3723-2 has a fixed blanking time of approximately
80ns. The nominal voltage on R
LEB
is 2V. If leading edge
blanking is not required, tie R
LEB
to V
REF
to disable.
FB (Pin 13/Pin 13): Error Amplifier Inverting Input. This is
the voltage feedback input for the LTC3723. The nominal
regulation voltage at FB is 1.2V.
