LTC3723-1/LTC3723-2
7
372312f
PROGRAMMABLE
DEAD-TIME
PROGRAMMABLE
SYNCHRONOUS
TURN-OFF DELAY
DRVA
DRVB
SDRA
SDRB
372312 TD01
CURRENT
SENSE
OR C
T
RAMP
PWM
COMPARATOR
(–)
TI I G DIAGRA
WUW
DESCRIPTIO S
U
PI
U
(LTC3723-1/LTC3723-2)
SS (Pin 14/Pin 14): Soft-Start/Restart Delay Circuitry
Timing Capacitor. A capacitor from SS to GND provides a
controlled ramp of the current command (LTC3723-1) or
duty cycle (LTC3723-2). During overload conditions, SS is
discharged to ground initiating a soft-start cycle. SS
charging current is approximately 13µA. SS will charge up
to approximately 5V in normal operation. During a con-
stant overload current fault, SS will oscillate at a low
frequency between approximately 0.5V and 4V.
UVLO (Pin 15/Pin 15): Input to Program System Turn-On
and Turn-Off Voltages. The nominal threshold of the UVLO
comparator is 5.0V. UVLO is connected to the main DC
system feed through a resistor divider. When the UVLO
threshold is exceeded, the LTC3723-1/LTC3723-2 com-
mences a soft-start cycle and a 10µA (nominal) current is
fed out of UVLO to program the desired amount of system
hysteresis. The hysteresis level can be adjusted by chang-
ing the resistance of the divider. UVLO can also be used to
terminate all switching by pulling UVLO down to less than
4V. An open drain or collector switch can perform this
function without changing the system turn on or turn off
voltages.
SPRG (Pin 16/Pin 16): A resistor is connected between
SPRG and GND to set the turn off delay for the synchro-
nous rectifier driver outputs. The nominal voltage on
SPRG is 2V.
