LTC3723EGN-2#TRPBF Datasheet LTC3723EGN-2#TRPBF, LTC3723EGN-1#TRPBF, LTC3723EGN-1#PBF | P13-P15

LTC3723-1/LTC3723-2

372312f

The 50% duty-cycle limit is overcome with the circuit

shown in Figure 7. Operation is similar to external syn-

chronization, except DRVA output is used to terminate its

own clock cycle early. Switching period is now equal to the

oscillator period plus programmable driver dead time.

Maximum on time is equal to oscillator period minus

driver dead time.

Although near 100% duty cycle operation may be of

benefit with non-isolated converters, it is often desirable

to limit the duty cycle of single-ended isolated converters.

Instead of immediately ending the unused clock’s output,

Figure 8 uses a transistor to switch in additional timing

capacitor charge current. This allows one to preset the

maximum duty.

Voltage Mode with LTC3723-2

Figure 9 shows how basic connections differ between

current mode LTC3723-1 and voltage mode LTC3723-2.

Oscillator may be used as the ramp input or the LTC3723-

2 includes an internal 10mA ramp discharge useful when

implementing voltage feedforward. Open loop control in

which the duty cycle varies inversely proportional to input

voltage is shown in Figure 10.

OPERATIO

LTC3723-1

DRVA

68pF

372312 F07

DRVB

390Ω

BAT54

DPRG

MAX SW

≅

⎛

⎝

⎜

⎞

⎠

⎟

≅

⎛

⎝

⎜

⎞

⎠

⎟

256

210

256

210

.•

–

Figure 7. LTC3723-1 > 50% Duty Cycle

LTC3723-1

DRVB

TO SYNCHRONOUS

SECONDARY MOSFET

372312 F08

•

SDRBDRVA

REF

–V

50k

MMBT2369

AAR

DPRG

MAX SW

≅

µ+

()

⎛

⎝

⎜

⎞

⎠

⎟

≅

⎛

⎝

⎜

⎞

⎠

⎟

256

210

210 3

256

210

.•

–

Figure 8. LTC3723-1 One-Switch Forward or Flyback Converter

(Maximum Duty Cycle 50% to 100%)

Figure 9. LTC3723-1 Current Mode and LTC3723-2 Voltage

Mode Connections

Figure 10. LTC3723-2 Open Loop Control (Duty Cycle is

Inversely Proportional to Input Voltage)

9811

372312 F10

TO INPUT

VOLTAGE

LTC3723-2

RAMPC

COMP

DPRG

98121

372312 F09

TO INPUT

VOLTAGE

LTC3723-2

RAMPC

DPRGV

REF

DPRG

12819

LEB

LTC3723-1

RLEBC

REF

DPRG

89121

LTC3723-2

RAMP DPRGV

REF

LTC3723-1/LTC3723-2

372312f

OPERATIO

The LTC3723-1 derives a compensating slope current

from the oscillator ramp waveform and sources this

current out of CS. This function is disabled in the

LTC3723-2. The desired level of slope compensation is

selected with an external resistor connected between CS

and the external current sense resistor, (Figure 11).

Current Sensing and Overcurrent Protection

Current sensing provides feedback for the current mode

control loop and protection from overload conditions. The

LTC3723-1/LTC3723-2 are compatible with either resis-

tive sensing or current transformer methods. Internally

connected to the LTC3723-1/LTC3723-2 CS pin are two

comparators that provide pulse-by-pulse and overcurrent

shutdown functions respectively, (Figure 12).

The pulse-by-pulse comparator has a 300mV nominal

threshold. If the 300mV threshold is exceeded, the PWM

cycle is terminated. The overcurrent comparator is set

approximately 2x higher than the pulse-by-pulse level. If

the current signal exceeds this level, the PWM cycle is

terminated, the soft-start capacitor is quickly discharged

and a soft-start cycle is initiated. If the overcurrent condi-

tion persists, the LTC3723-1/LTC3723-2 halts PWM op-

eration and waits for the soft-start capacitor to charge up

to approximately 4V before a retry is allowed. The soft-

start capacitor is charged by an internal 13µA current

source. If the fault condition has not cleared when soft-

start reaches 4V, the soft-start pin is again discharged and

a new cycle is initiated. This is referred to as hiccup mode

operation. In normal operation and under most abnormal

conditions, the pulse-by-pulse comparator is fast enough

to prevent hiccup mode operation. In severe cases, how-

ever, with high input voltage, very low R

DS(ON)

MOSFETs

and a shorted output, or with saturating magnetics, the

overcurrent comparator provides a means of protecting

the power converter.

Leading Edge Blanking

The LTC3723-1/LTC3723-2 provides programmable lead-

ing edge blanking to prevent nuisance tripping of the

current sense circuitry. Leading edge blanking relieves the

filtering requirements for the CS pin, greatly improving the

response to real overcurrent conditions. It also allows the

use of a ground referenced current sense resistor or

transformer(s), further simplifying the design. With a

single 10k to 100k resistor from R

LEB

to GND, blanking

times of approximately 40ns to 320ns are programmed. If

not required, connecting R

LEB

to V

REF

can disable leading

edge blanking. Keep in mind that the use of leading edge

blanking will slightly reduce the linear control range for the

pulse width modulator.

Figure 12. Current Sense/Fault Circuitry Detail

–

OVERLOAD

CURRENT LIMIT

300mV

600mV

UVLO

ENABLE

UVLO

ENABLE

PWM

LOGIC

H = SHUTDOWN

OUTPUTS

–

0.4V

4.1V

372312 F12

PULSE BY PULSE

CURRENT LIMIT

PWM

LATCH

PWM

13µA

Figure 11. Slope Compensation Circuitry

SWITCH

CURRENT

CURRENT SENSE

WAVEFORM

V(C

)

33k

I =

33k

ADDED

SLOPE

372312 F11

LTC3723

LTC3723-1/LTC3723-2

372312f

OPERATIO

High Current Drivers

The LTC3723-1/LTC3723-2 high current, high speed driv-

ers provide direct drive of external power N-channel

MOSFET switches. The drivers swing from rail to rail. Due

to the high pulsed current nature of these drivers (1.5A

sink, 1A source), care must be taken with the board layout

to obtain advertised performance. Bypass V

with a 1µF

minimum, low ESR, ESL ceramic capacitor. Connect this

capacitor with minimal length PCB leads to both V

and

GND. A ground plane is highly recommended. The driver

output pins (DRVA, DRVB) connect to the gates of the

external MOSFET switches. The PCB traces making these

connections should also be as short as possible to mini-

mize overshoot and undershoot of the drive signal.

Synchronous Rectification

The LTC3723-1/LTC3723-2 produces the precise timing

signals necessary to control secondary side synchronous

rectifier MOSFETs on SDRA and SDRB. Synchronous

rectifiers are used in place of Schottky or silicon diodes on

the secondary side to improve converter efficiency. As

MOSFET R

DS(ON)

levels continue to drop, significant effi-

ciency improvements can be realized with synchronous

rectification, provided that the MOSFET switch timing is

optimized. Synchronous rectification also provides bipo-

lar output current capability, that is, the ability to sink as

well as source current.

Programming the Synchronous Rectifier

Turn-Off Delay

The LTC3723-1/LTC3723-2 controllers include a feature

to program the turn-off edge of the secondary side syn-

chronous rectifier MOSFETs relative to the beginning of a

new primary side power delivery pulse. This feature pro-

vides optimized timing for the synchronous MOSFETs

which improves efficiency. At higher load currents it

becomes more advantageous to delay the turn-off of the

synchronous rectifiers until the beginning of the new

power pulse. This allows for secondary freewheeling

current to flow through the synchronous MOSFET channel

instead of its body diode.

The turn-off delay is programmed with a resistor from

SPRG to GND, (Figure 13). The nominal regulated voltage

on SPRG is 2V. The external resistor programs a current

which flows out of SPRG. The delay can be adjusted from

approximately 20ns to 200ns, with resistor values of 10k

to 200k. Do not leave SPRG floating. The amount of delay

can also be modulated based on an external current

source that sinks current out of SPRG. Care must be taken

to limit the current out of SPRG to 350µA or less.

–

TURN-OFF

SYNC OUT

372312 F13

–

SPRG

Figure 13. Synchronous Delay Circuitry

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

LTC3723EGN-2#TRPBF

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