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PCA9500PW,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
PCA9500 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 4.1 — 5 May 2017 16 of 29
NXP Semiconductors
PCA9500
8-bit I
2
C-bus and SMBus I/O port with 2-kbit EEPROM
11. Static characteristics
[1] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
Table 5. Static characteristics
Symbol Parameter Conditions Min Typ Max Unit
Supply
V
DD
supply voltage 2.5 3.3 3.6 V
I
DDQ
standby current A0, A1, A2, WC =HIGH - - 60 A
I
DD1
supply current read - - 1 mA
I
DD2
supply current write - - 2 mA
V
POR
power-on reset voltage - - 2.4 V
Input SCL; input/output SDA
V
IL
LOW-level input voltage 0.5 - +0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-5.5V
I
OL
LOW-level output current V
OL
=0.4V 3 - - mA
I
LI
input leakage current V
I
=V
DD
or V
SS
1-+1A
C
i
input capacitance V
I
=V
SS
--7pF
I/O expander port
V
IL
LOW-level input voltage 0.5 - +0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-5.5V
I
IHL(max)
input current through protection diodes 400 - +400 A
I
OL
LOW-level output current V
OL
=1V
[1]
10 25 - mA
I
OH
HIGH-level output current V
OH
=V
SS
30 100 300 A
I
OHt
transient pull-up current - 2 - mA
C
i
input capacitance - - 10 pF
C
o
output capacitance - - 10 pF
Address inputs A0, A1, A2; WC
input
V
IL
LOW-level input voltage 0.5 - +0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-5.5V
I
LI
input leakage current V
I
=V
DD
1-+1A
pull-up; V
I
=V
SS
10 25 100 A
PCA9500 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 4.1 — 5 May 2017 17 of 29
NXP Semiconductors
PCA9500
8-bit I
2
C-bus and SMBus I/O port with 2-kbit EEPROM
Remark: Rapid fall-off in V
OH
at current inception is due to a diode that provides 5 V
overvoltage protection for the GPIO I/O pins. When the GPIO I/O are being used as
inputs, the internal current source V
OH
should be evaluated to determine if external pull-up
resistors are required to provide sufficient V
IH
threshold noise margin.
a. T
amb
= 40 Cb.T
amb
=25C
c. T
amb
=85C
Fig 21. V
OH
versus I
OH
−160
−40
20
I
OH
(μA)
V
OH
(V)
0 3.61.2 2.4
002aad307
V
DD
= 2.5 V
2.7 V
3.0 V
3.3 V
3.6 V
−100
−140
−20
−60
−100
20
I
OH
(μA)
V
OH
(V)
0 3.61.2 2.4
002aad308
V
DD
= 2.5 V
2.7 V
3.0 V
3.3 V
3.6 V
−140
−20
−60
−100
20
I
OH
(μA)
V
OH
(V)
0 3.61.2 2.4
002aad309
V
DD
= 2.5 V
2.7 V
3.0 V
3.3 V
3.6 V
PCA9500 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 4.1 — 5 May 2017 18 of 29
NXP Semiconductors
PCA9500
8-bit I
2
C-bus and SMBus I/O port with 2-kbit EEPROM
12. Dynamic characteristics
[1] All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
IL
and V
IH
with an input
voltage swing of V
SS
to V
DD
.
[2] t
pu(R)
and t
pu(W)
are the delays required from the time V
DD
is stable until the specified operation can be initiated. These parameters are
guaranteed by design.
[3] T
cy(W)
is the maximum time that the device requires to perform the internal write operation.
Table 6. Dynamic characteristics
Symbol Parameter Conditions Min Typ Max Unit
I
2
C-bus timing
[1]
(see Figure 22)
f
SCL
SCL clock frequency - - 400 kHz
t
SP
pulse width of spikes that must be
suppressed by the input filter
- - 50 ns
t
BUF
bus free time between a STOP and START
condition
1.3 - - s
t
SU;STA
set-up time for a repeated START condition 0.6 - - s
t
HD;STA
hold time (repeated) START condition 0.6 - - s
t
r
rise time of both SDA and SCL signals - - 0.3 s
t
f
fall time of both SDA and SCL signals - - 0.3 s
t
SU;DAT
data set-up time 250 - - ns
t
HD;DAT
data hold time 0 - - ns
t
VD;DAT
data valid time SCL LOW to
data output
--1.0s
t
SU;STO
set-up time for STOP condition 0.6 - - s
Port timing
t
v(Q)
data output valid time C
L
100 pF - - 4 s
t
su(D)
data input set-up time C
L
100 pF 0 - - s
t
h(D)
data input hold time C
L
100 pF 4 - - s
Power-up timing
t
pu(R)
read power-up time
[2]
--1ms
t
pu(W)
write power-up time
[2]
--5ms
Write cycle limits (see Figure 23
)
T
cy(W)
write cycle time
[3]
-510ms
Table 7. Non-volatile storage specifications
Parameter Specification
memory cell data retention 10 years minimum
number of memory cell write cycles 100,000 cycles minimum
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

PCA9500PW,112

Mfr. #:
Buy PCA9500PW,112
Manufacturer:
NXP Semiconductors
Description:
Interface - I/O Expanders I/O EXPANDER W/2K EE
Lifecycle:
New from this manufacturer.
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