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PCA9500PW,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
PCA9500 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 4.1 — 5 May 2017 7 of 29
NXP Semiconductors
PCA9500
8-bit I
2
C-bus and SMBus I/O port with 2-kbit EEPROM
7. Functional description
Refer also to Figure 1 “Block diagram of PCA9500”.
7.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9500 is shown in Figure 6
. Internal pull-up resistors
are incorporated on the hardware selectable address pins.
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
7.2 Control register
The PCA9500 contains a single 8-bit register called the Control register, which can be
written and read via the I
2
C-bus. This register is sent after a successful acknowledgment
of the slave address. It contains the I/O operation information.
Fig 5. Simplified schematic diagram of each I/O
002aae588
write pulse
read pulse
D
CI
S
FF
Q
power-on reset
data from shift register
100 μA
V
DD
IO0 to IO7
V
SS
D
CI
S
FF
Q
data to shift register
to interrupt logic
a. I/O expander b. Memory
Fig 6. PCA9500 slave addresses
002aae589
0 1 0 0 A2 A1 A0 R/W
fixed
slave address
hardware
programmable
PCA9500 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 4.1 — 5 May 2017 8 of 29
NXP Semiconductors
PCA9500
8-bit I
2
C-bus and SMBus I/O port with 2-kbit EEPROM
7.3 I/O operations
(Refer also to Figure 5.)
Each of the PCA9500's eight I/Os can be independently used as an input or output.
Output data is transmitted to the port by the I/O Write mode (see Figure 7
). Input I/O data
is transferred from the port to the microcontroller by the Read mode (see Figure 8
).
Fig 7. I/O Write mode (output)
0 AS
slave address (I/O expander)
START condition R/W acknowledge
from slave
002aae591
DATA 1
data to port
A
acknowledge
from slave
12345678SCL 9
SDA
DATA 2 A
write to port
data out from port
t
v(Q)
acknowledge
from slave
DATA 2 VALID
data to port
1 0 0 A2 A1 A00
DATA 1 VALID
t
v(Q)
Fig 8. I/O Read mode (input)
1 0 0 A2 A1 A0 1 AS0
slave address (I/O expander)
START condition R/W
acknowledge
from slave
002aae592
data from port
A
acknowledge
from master
SDA 1
no acknowledge
from master
read from
port
data into
port
data from port
DATA 1
DATA 4
DATA 4
DATA 2
DATA 3
P
STOP
condition
t
h(D)
t
su(D)
12345678SCL 9
DATA 1
PCA9500 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 4.1 — 5 May 2017 9 of 29
NXP Semiconductors
PCA9500
8-bit I
2
C-bus and SMBus I/O port with 2-kbit EEPROM
7.3.1 Quasi-bidirectional I/Os
A quasi-bidirectional I/O can be used as an input or output without the use of a control
signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current
source to V
DD
is active. An additional strong pull-up to V
DD
allows fast rising edges into
heavily loaded outputs. These devices turn on when an output is written HIGH, and are
switched off by the negative edge of SCL. The I/Os should be HIGH before being used as
inputs. See Figure 9
.
7.4 Memory operations
7.4.1 Write operations
Write operations require an additional address field to indicate the memory address
location to be written. The address field is eight bits long, providing access to any one of
the 256 words of memory. There are two types of write operations, ‘byte write’ and
‘page write’.
Write operation is possible when the Write Control pin (WC
) is put at a LOW logic level (0).
When this control signal is set at 1, write operation is not possible and data in the memory
is protected.
‘Byte write’ and ‘page write’ explained below assume that WC
is set to 0.
7.4.1.1 Byte write
To perform a byte write the START condition is followed by the memory slave address and
the R/W
bit set to 0. The PCA9500 will respond with an acknowledge and then consider
the next eight bits sent as the word address and the eight bits after the word address as
the data. The PCA9500 will issue an acknowledge after the receipt of both the word
address and the data. To terminate the data transfer the master issues the STOP
condition, initiating the internal write cycle to the non-volatile memory. Only write and read
operations to the quasi-bidirectional I/Os are allowed during the internal write cycle.
Fig 9. Transient pull-up current (I
OHt
) while IO3 changes from LOW to HIGH and back to LOW
0 AS
slave address (I/O expander)
START condition R/W acknowledge
from slave
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1
data to port
A
acknowledge
from slave
12345678SCL 9
SDA
0 A
IO3 output voltage
IO3 pull-up output current
acknowledge
from slave
data to port
1 0 0 A2 A1 A00
IO3
P
STOP
condition
IO3
I
OHt
I
OH
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PCA9500PW,112

Mfr. #:
Buy PCA9500PW,112
Manufacturer:
NXP Semiconductors
Description:
Interface - I/O Expanders I/O EXPANDER W/2K EE
Lifecycle:
New from this manufacturer.
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