PCF2003 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1 — 20 October 2015 4 of 30
NXP Semiconductors
PCF2003
32 kHz watch circuit with programmable adaptive motor pulse
If a missing step is detected, a correction sequence is generated (see Figure 3) and the
driving stage is switched to the next level. The correction sequence consists of two
pulses: first a short pulse in the opposite direction (0.98 ms, modulated with the maximum
duty cycle) to give the motor a defined position, followed by a motor pulse of the strongest
driving level. Every 4 minutes, the driving level is lowered again by one stage.
The motor pulse has a constant pulse width. The driving level is regulated by chopping the
driving pulse with a variable duty cycle. The driving level starts from the programmed
minimum value and increases by 6.25 % after each failed motor step. The strongest
driving stage, which is not followed by a detection phase, is programmed separately.
Therefore, it is possible to program a larger energy gap between the pulses with step
detection and the strongest, not monitored, pulse. This might be necessary to ensure a
reliable and stable operation under adverse conditions (magnetic fields and vibrations). If
the watch works in the highest driving stage, the driving level jumps after the 4-minute
period directly to the lowest stage, and not just one stage lower.
To optimize the performance for different motors, the following parameters can be
programmed:
Pulse width: 0.98 ms to 7.8 ms in steps of 0.98 ms
Duty cycle of lowest driving level: 37.5 % to 56.25 % in steps of 6.25 %
Number of driving levels (including the highest driving level): 3 to 6
Duty cycle of the highest driving level: 75 % or 100 %
Enlargement pulse for the highest driving level: on or off
The enlargement pulse has a duty cycle of 25 % and a pulse width which is twice the
programmed motor pulse width. The repetition period for the chopping pattern is 0.98 ms.
Figure 4
shows an example of a 3.9 ms pulse.
Fig 3. Correction sequence after failed motor step
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PCF2003 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1 — 20 October 2015 5 of 30
NXP Semiconductors
PCF2003
32 kHz watch circuit with programmable adaptive motor pulse
Fig 4. Possible modulations for a 3.9 ms motor pulse
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PCF2003 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1 — 20 October 2015 6 of 30
NXP Semiconductors
PCF2003
32 kHz watch circuit with programmable adaptive motor pulse
7.2 Step detection
Figure 5 shows a simplified diagram of the motor driving and step detection circuit, and
Figure 6
shows the step detection sequence and corresponding sampling current.
Between the motor driving pulses, the switches P1 and P2 are closed, which means the
motor is short-circuited. For a pulse in one direction, P1 and N2 are open, and P2 and N1
are closed with the appropriate duty cycle; for a pulse in the opposite direction, P2 and N1
are open, and P1 and N2 closed.
The step detection phase is initiated after the motor driving pulse. In phase 1 P1 and P2
are first closed for 0.98 ms and then in phase 2 all four drive switches (P1, N1, P2 and N2)
are opened for 0.98 ms. As a result, the energy stored in the motor inductance is reduced
as fast as possible.
The induced current caused by the residual motor movement is then sampled in phase 3
(closing P3 and P2) and in phase 4 (closing P1 and P4). For step detection in the opposite
direction P1 and P4 are closed during phase 3 and P2 and P3 during phase 4 (see
Figure 6
).
Fig 5. Simplified diagram of motor driving and step detection circuit
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PCF2003DUS/DAAZ

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC CLOCK 32KHZ 1CIR 8WLCSP
Lifecycle:
New from this manufacturer.
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