PCF2003 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1 — 20 October 2015 7 of 30
NXP Semiconductors
PCF2003
32 kHz watch circuit with programmable adaptive motor pulse
The condition for a successful motor step is a positive step detection pulse (current in the
same direction as in the driving phase) followed by a negative detection pulse within a
given time limit. This time limit can be programmed between 3.9 ms and 10.7 ms (in steps
of 0.98 ms) in order to ensure a safe and correct step detection under all conditions (for
instance magnetic fields). The step detection phase stops after the last 31.25 ms, after the
start of the motor driving pulse.
7.3 Time calibration
The quartz crystal oscillator has an integrated capacitance of 5.2 pF, which is lower than
the specified capacitance (C
L
) of 8.2 pF for the quartz crystal (see Table 11). Therefore,
the oscillator frequency is typically 60 ppm higher than 32.768 kHz. This positive
frequency offset is compensated by removing the appropriate number of 8192 Hz pulses
in the divider chain (maximum 127 pulses), every 1 or 2 minutes. The time correction is
given in Table 4
.
After measuring the effective oscillator frequency, the number of correction pulses must
be calculated and stored together with the calibration period in the OTP memory (see
Section 7.7
).
Fig 6. Step detection sequence and corresponding sampling voltage
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Table 4. Time calibration
Calibration
period
Correction per step (n = 1) Correction per step (n = 127)
ppm Seconds per day ppm Seconds per day
1 minute 2.03 0.176 258 22.3
2 minutes 1.017 0.088 129 11.15
PCF2003 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1 — 20 October 2015 8 of 30
NXP Semiconductors
PCF2003
32 kHz watch circuit with programmable adaptive motor pulse
The oscillator frequency can be measured at pad RESET, where a square wave signal
with the frequency of is provided. This frequency shows a jitter every minute or
every two minutes, which originates from the time calibration, depending on the
programmed calibration period.
Details on how to measure the oscillator frequency and the programmed inhibition time
are given in Section 7.10
.
7.4 Reset
At pad RESET an output signal with a frequency of is provided.
Connecting pad RESET to V
DD
stops the motor drive and opens all four (P1, N1, P2 and
N2) driver switches (see Figure 5
). Connecting pad RESET to V
SS
activates the test
mode. In this mode the motor output frequency is 32 Hz, which can be used to test the
mechanical function of the watch.
After releasing the pad RESET, the motor starts exactly one second later with the smallest
duty cycle and with the opposite polarity to the last pulse before stopping. The debounce
time for the RESET function is between 31 ms and 62 ms.
7.5 Programming possibilities
The programming data is stored in OTP cells (EPROM cells). At delivery, all memory cells
are in state 0. The cells can be programmed to the state 1, but then there is no more set
back to state 0. The programming data is organized in an array of four 8-bit words
(see Table 5
): word A contains the time calibration, words B and C contain the setting for
the motor pulses and word D contains the type recognition.
1
1024
------------
f
osc
32 Hz=
Table 5. Words and bits
Word Bit
1 2 3 4 5 6 7 8
A number of 8192 Hz pulses to be removed calibration
period
B lowest stage: duty cycle number of driving stages highest
stage: duty
cycle
pulse
stretching
output period
C pulse width maximum time delay between positive
and negative detection pulses
output
period
factory test
bit
D type factory test bits
Table 6. Description of word A bits
Bit Value Description
Inhibition time
1 to 7 - adjust the number of the 8192 Hz pulses to be removed;
bit 1 is the MSB and bit 7 is the LSB
Calibration period
801minute
12minutes
PCF2003 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1 — 20 October 2015 9 of 30
NXP Semiconductors
PCF2003
32 kHz watch circuit with programmable adaptive motor pulse
[1] Including the highest driving stage, which one has no motor step detection.
[2] If the maximum duty cycle of 75 % is selected, not all programming combinations are possible since the
second highest level must be smaller than the highest driving level.
Table 7. Description of word B bits
Bit Value Description
Duty cycle lowest driving stage
1to2 00 37.5 %
01 43.75 %
10 50 %
11 56.25 %
Number of driving stages
3to4 00 3
01 4
10 5
11 6
[1]
Duty cycle highest driving stage
5075 %
[2]
1100 %
Pulse stretching
6 0 no pulse stretching
1 pulse of 2 t
p
and duty cycle of 25 % are added
Output period
7to8 00 1 s
01 5 s
10 10 s
11 20 s

PCF2003DUS/DAAZ

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC CLOCK 32KHZ 1CIR 8WLCSP
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