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X28HC256PIZ-90

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
X28HC256
13
FN8108.5
August 27, 2015
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Software Data Protection
Regardless of whether the device has previously been protected
or not, once the software data protection algorithm is used and
data has been written, the X28HC256 will automatically disable
further writes unless another command is issued to cancel it. If
no further commands are issued the X28HC256 will be write
protected during power-down and after any subsequent
power-up.
Note: Once initiated, the sequence of write operations should not
be interrupted.
Resetting Software Data
Protection
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an EEPROM
programmer, the following six step algorithm will reset the
internal protection circuit. After t
WC
, the X28HC256 will be in
standard operating mode.
Note: Once initiated, the sequence of write operations should not
be interrupted.
CE
WE
(V
CC
)
WRITE
PROTECTED
V
CC
0V
DATA
ADDRESS
AA
5555
55
2AAA
A0
5555
£t
BLC MAX
WRITES
OK
BYTE
OR
AGE
t
WC
FIGURE 12. TIMING SEQUENCE BYTE OR PAGE WRITE
WRITE LAST
WRITE DATA XX
TO ANY
WRITE DATA A0
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA AA
TO ADDRESS
5555
AFTER t
WC
RE-ENTERS DATA
PROTECTED STATE
BYTE TO
LAST ADDRESS
ADDRESS
OPTIONAL
BYTE/PAGE
LOAD OPERATION
BYTE/PAGE
LOAD ENABLED
FIGURE 13. WRITE SEQUENCE FOR SOFTWARE DATA
PROTECTION
X28HC256
14
FN8108.5
August 27, 2015
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System Considerations
Because the X28HC256 is frequently used in large memory
arrays, it is provided with a two line control architecture for both
read and write operations. Proper usage can provide the lowest
possible power dissipation and eliminate the possibility of
contention where multiple I/O pins share the same bus.
To gain the most benefit, it is recommended that CE
be decoded
from the address bus and be used as the primary device
selection input. Both OE
and WE would then be common among
all devices in the array. For a read operation, this assures that all
deselected devices are in their standby mode and that only the
selected device(s) is/are outputting data on the bus.
Because the X28HC256 has two power modes, standby and
active, proper decoupling of the memory array is of prime
concern. Enabling CE
will cause transient current spikes. The
magnitude of these spikes is dependent on the output capacitive
loading of the l/Os. Therefore, the larger the array sharing a
common bus, the larger the transient spikes. The voltage peaks
associated with the current transients can be suppressed by the
proper selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high frequency
ceramic capacitor be used between V
CC
and V
SS
at each device.
Depending on the size of the array, the value of the capacitor
may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic bulk
capacitor be placed between V
CC
and V
SS
for each eight devices
employed in the array. This bulk capacitor is employed to
overcome the voltage droop caused by the inductive effects of
the PC board traces.
CE
WE
STANDARD
OPERATING
MODE
V
CC
DATA
ADDRESS
AA
5555
55
2AAA
80
5555
t
WC
AA
5555
55
2AAA
20
5555
FIGURE 14. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 80
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 20
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
AFTER t
WC
,
RE-ENTERS
UNPROTECTED
STATE
FIGURE 15. WRITE SEQUENCE FOR RESETTING SOFTWARE DATA
PROTECTION
X28HC256
15
FN8108.5
August 27, 2015
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About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask
.
Reliability reports are also available from our website at www.intersil.com/support
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE REVISION CHANGE
August 27, 2015 FN8108.5 Removed the reference to Military part under “Recommended Operating Conditions” and “Thermal Information”
Removed X28HC256J-15, X28HC256SI-15, X28HC256SIZ-15, X28HC256J-12, X28HC256S-12, and
X28HC256S-90 from the Ordering Information table on page 2.
Updated Pin Description table on page 3.
March 31, 2015 FN8108.4 -Updated entire datasheet to Intersil new standard.
-Added revision history and about Intersil verbiage.
-Third paragraph on page 1 updated From:
Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data
retention of 100 years.
To:
Endurance for the X28HC256 is specified as a minimum 100,000 write cycles per byte and an inherent data
retention of 100 years.
-Features section on page 1 updated From:
Highly reliable Direct Write™ cell
- Endurance: 1,000,000 cycles
To:
Highly reliable Direct Write™ cell
- Endurance: 100,000 cycles
“Endurance and Data Retention” on page 4 updated Endurance from 1,000,000 to 100,000.
-Ordering information table on page 2: Removed obsolete part numbers X28HC256P-15, X28HC256PI-15,
X28HC256P-12, X28HC256PI-12, X28HC256P-90.
-Ordering information table on page 2 updated the “Access time’ section.
Thermal Information table on page 4 updated “Temperature Under Bias” section for X28HC256 value from 10°C
to +85°C to -10°C to +85°C.
“DC Electrical Specifications” on page 4, added a note to Min and Max values.
Removed note in Electrical Spec Table that referenced an obsolete part.
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X28HC256PIZ-90

Mfr. #:
Buy X28HC256PIZ-90
Manufacturer:
Renesas / Intersil
Description:
EEPROM 32K X 8 EEPROM,CMOS,HIGH SPEED,PDIP,I.TEMP,90NS,PB FREE
Lifecycle:
New from this manufacturer.
Delivery:
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