X28HC256
7
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August 27, 2015
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WE Controlled Write Cycle
CE
Controlled Write Cycle
S
ADDRESS
t
AS
t
WC
t
AH
t
OES
t
DS
t
DH
t
OEH
CE
WE
OE
DATA IN
DATA OUT
HIGH Z
DATA VALID
t
CS
t
CH
t
WP
FIGURE 4. WE CONTROLLED WRITE CYCLE
ADDRESS
t
AS
t
OEH
t
WC
t
AH
t
OES
t
CS
t
DS
t
DH
t
CH
CE
WE
OE
DATA IN
DATA OUT
HIGH Z
DATA VALID
t
CW
FIGURE 5. CE CONTROLLED WRITE CYCLE
X28HC256
8
FN8108.5
August 27, 2015
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Page Write Cycle
WE
OE
LAST BYTE
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n + 1 BYTE n + 2
t
WP
t
WPH
t
BLC
t
WC
CE
ADDRESS
I/O
OE
(Note 13)
(Note 14, 15)
NOTES:
13. Between successive byte writes within a page write operation, OE
can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data
from another memory device within the system for the next write; or with WE
HIGH and CE LOW effectively performing a polling operation.
14. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE
or WE
controlled write cycle timing.
15. For each successive write within the page write operation, A7 to A15 should be the same or writes to an unknown address could occur.
FIGURE 6. PAGE WRITE CYCLE
X28HC256
9
FN8108.5
August 27, 2015
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DATA Polling Timing Diagram
(Note 16)
Toggle Bit Timing Diagram
(Note 16)
ADDRESS A
n
D
IN
= X
t
WC
t
OEH
t
OES
CE
WE
OE
I/O
7
t
DW
A
n
A
n
D
OUT
= X D
OUT
= X
FIGURE 6. DATA POLLING TIMING DIAGRAM
CE
OE
WE
I/O
6
t
OES
t
DW
t
WC
t
OEH
HIGH Z
(Note 17)
(
Note 17)
NOTES:
16. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
17. I/O
6
beginning and ending state will vary, depending upon actual t
WC
.
FIGURE 7. TOGGLE BIT TIMING DIAGRAM

X28HC256PIZ-90

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
EEPROM 32K X 8 EEPROM,CMOS,HIGH SPEED,PDIP,I.TEMP,90NS,PB FREE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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