Data Sheet ADF5901
Rev. A | Page 11 of 26
THEORY OF OPERATION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 14. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This configuration ensures that there is no loading of
the REF
IN
pin on power-down.
Figure 14. Reference Input Stage
RF INT DIVIDER
The RF INT counter allows a division ratio in the RF feedback
counter. Division ratios from 75 to 4095 are allowed.
INT, FRAC, AND R RELATIONSHIP
Generate the RF VCO frequency (RF
OUT
) using the INT and
FRAC values in conjunction with the R counter, as follows:
RF
OUT
= f
REF
× (INT + (FRAC/2
25
)) × 2 (1)
where:
RF
OUT
is the output frequency of internal VCO.
f
REF
is the internal reference frequency.
INT is the preset divide ratio of the binary 12-bit counter
(75 to 4095).
FRAC is the numerator of the fractional division (0 to 2
25
− 1).
f
REF
= REF
IN
× ((1 + D)/(R × (1 + T))) (2)
where:
REF
IN
is the reference input frequency.
D is the REF
IN
doubler bit (0 or 1).
R is the preset divide ratio of the binary, 5-bit, programmable
reference counter (1 to 32).
T is the REF
IN
divide by 2 bit (0 or 1).
Figure 15. RF N Divider
Figure 16. Reference Divider
R COUNTER
The 5-bit R counter allows the input reference frequency (REF
IN
)
to be divided down to supply the reference clock to the VCO
calibration block. Division ratios from 1 to 32 are allowed.
INPUT SHIFT REGISTER
The ADF5901 digital section includes a 5-bit RF R counter,
a 12-bit RF N counter, and a 25-bit FRAC counter. Data is
clocked into the 32-bit input shift register on each rising edge of
CLK. The data is clocked in MSB first. Data is transferred from
the input shift register to one of 12 latches on the rising edge of
LE. The destination latch is determined by the state of the five
control bits (C5, C4, C3, C2, and C1) in the input shift register.
These are the five LSBs (DB4, DB3, DB2, DB1, and DB0,
respectively), as shown in Figure 2. Table 5 shows the truth table
for these bits. Figure 17 and Figure 18 show a summary of how
the latches are programmed.
PROGRAM MODES
Table 5 and Figure 19 through Figure 30 show how to set up the
program modes in the ADF5901.
Several settings in the
ADF5901 are double buffered. These
include the LSB fractional value, R counter value (R divider),
reference doubler, clock divider, RDIV2, and MUXOUT. This
means that two events must occur before the device uses a new
value for any of the double-buffered settings. First, the new
value is latched into the device by writing to the appropriate
register. Second, a new write must be performed on Register R5.
For example, updating the fractional value can involve a write to
the 13 LSB bits in Register R6 and the 12 MSB bits in Register R5.
Write to Register R6 first, followed by the write to Register R5.
The frequency change begins after the write to Register R0.
Double buffering ensures that the bits written to in Register R6
do not take effect until after the write to Register R5.
BUFFER
TO R COUNTER
REF
IN
100kΩ
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
13336-014
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
INT
REG
RF N DIVIDER
N = INT + FRAC/2
25
FROM RF
INPUT ST
AGE
TO CAL
BLOCK
N COUNTER
13336-015
×2
DOUBLER
5-BIT
R COUNTER
÷2
DIVIDER
TO CAL
BLOCK
REF
IN
R DIVIDER
13336-016
