ADF5901ACPZ Datasheet ADF5901ACPZ, ADF5901WCCPZ, ADF5901WCCPZ-RL7 | P19-P21

ADF5901 Data Sheet

Rev. A | Page 18 of 26

Figure 22. Register 3 (R3)

REGISTER 3

Control Bits

With Bits[C5:C1] set to 00011, Register R3 is programmed.

Figure 22 shows the input data format for programming this

register.

MUXOUT Control

Bits[DB15:DB12] control the on-chip multiplexer of the

ADF5901. See Figure 22 for the truth table.

Input/Output (IO) Level

Bit DB11 controls the DOUT logic levels. Setting this bit to 0 sets

the DOUT logic level to 1.8 V. Setting this bit to 1 sets the DOUT

logic level to 3.3 V.

Readback Control

Bits[DB10:DB5] control the readback data to DOUT on the

ADF5901. See Figure 22 for the truth table.

DB31 DB30

DB29

DB28

DB27

DB26

DB25

DB24 DB23 DB22

DB21 DB20

DB19 DB18

DB17

DB16 DB15

DB14 DB13

DB12

DB1

1 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3 DB2 DB1 DB0

0 0

0

0 0

1

1 0

0

1

0

1

M3 M2 M1 M0

IOL

RC5

RC4 RC3

RC2 RC1

RC0

C4(0) C3(0)

C2(1) C1(1)

CONTROL

BITS

RESER

VED

C5(0)

READBACK CONTRO L

IO LEVE

L

RC3

RC2 RC1

RC0

READBACK CONTRO

L

0 0 0 0

NONE

0

0 1

REGISTER 0

0

0 1

0

REGISTER 1

0 0

1

REGISTER 2

0 1

0

REGISTER 3

0 1

REGISTER 4

0 1

1

0

REGSITER 5

0

1

1 1

REGISTER 6

1

0

0 0

REGISTER 7

1

0 0

1

REGISTER 8

1

0

1 0 REGISTER 9

1

0 1

1

REGISTER 10

1

1 0

0

REGISTER1

1

. .

.

. RESE

RVED

0 1

0

1 RESE

RVED

0

1 1

0 ADC READBACK

RC4

0

.

1

0 1

1 1

RESE

RVED

. . . .

RESE

RVED

.

. . . RESE

RVED

1

1 1

1

RESER

VED

1

.

1

M3

M2

M1

M0

MUXOUT

0

TRIS

TA

TE OUTPUT

0 0

0 1

LOGIC HIGH

0 0

1

0 LOGIC LOW

0 0

1

1 R-DIVIDER OUTPUT

0

1

0 0

N-DIVIDER OUTPUT

0

1

0 1

RESER

VED

0

1 1

0

RESER

VED

0

1 1

1

CAL

BUSY

1 0

0

0 RESE

R

VED

1 0

0

1 RESE

RVED

1

0 1

0

RESER

VED

1 0

1 1

R-DIVIDER/2

1 1

0

0 N-DIVIDER/2

1 1

0

1 RESE

RVED

1 1 1

0 RESE

R

VED

1

1 1 1 RESE

RVED

RC5

0

.

0

.

1

IOL

0

1

IO LEVEL

3.3V LOGIC OUTPUTS

1.8V LOGIC OUTPUTS

1

DBR = DOUBLE-BUFFERED REGISTER.

MUXOUT DBR

1

10849-022

Data Sheet ADF5901

Rev. A | Page 19 of 26

Figure 23. Register 4 (R4)

Figure 24. Register 5 (R5)

REGISTER 4

Control Bits

With Bits[C5:C1] set to 00100, Register R4 is programmed.

Figure 23 shows the input data format for programming this

register.

N Divider to MUXOUT Enable

Bit DB21 controls the internal N divider signal for MUXOUT.

Setting this bit to 0 enables the internal N divider signal to

MUXOUT. Setting this bit to 1 returns the device to normal

operation.

Test Bus to ADC

Bit DB16 controls the ATEST pin. Set this bit to 0 for normal

operation. Setting this bit to 1 connects the analog test bus to

the ADC input.

Test Bus to Pin

Bit DB15 controls the ATEST pin. Setting this bit to 0 sets the

ATEST pin to high impedance. Setting this bit to 1 connects the

analog test bus to the ATEST pin.

Analog Test Bus

Bits[DB14:DB5] control the analog test bus. This analog test bus

allows access to internal test signals for the temperature sensor.

See Figure 23 for the truth table.

REGISTER 5

Control Bits

With Bits[C5:C1] set to 00101, Register R5 is programmed.

Figure 24 shows the input data format for programming this

register.

DB31 DB30 DB29

DB28 DB27

DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

DB7 DB6

DB5

DB4 DB3 DB2 DB1 DB0

0 0 0 0

0

0 0

0

AB9

AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 C4(0)

C3(1)

C2(0) C1(0)

CONTROL

BITS

RESERVED RESERVED

TEST BUS

TO PIN

0 0 NDM 0 0 0 0 TBA TBP

ANALOG TEST BUS

C5(0)

TEST BUS

TO ADC

TBP

0

1

TEST BUS TO PIN

NORMAL OPERATION

NDM

0

1

N DIV TO MUXOUT EN

NORMAL OPERATION

ENABLE NDIV TO MUXOUT

TBA

0

1

TEST BUS TO ADC

NORMAL OPERATION

AB3 AB2 AB1 AB0

0 0 0 0

0 0 1 1

ANALOG TEST BUSAB7 AB6 AB5 AB4

0

0 0 0

0 0 0 0

AB9 AB8

0 0

0 1

0

259

NONE

TEMPERATURE SENSOR

13336-023

N DIV TO

MUXOUT EN

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 C4(0) C3(1) C2(0) C1(1)

CONTROL

BITS

RESERVED FRAC MSB WORDINTEGER WORD

C5(0)

N11 N10 ... N4 N3 N2 N1 N0

0 0 ... 0 0 0 0 0 NOT ALLOWED

0 0 ... 0 0 0 0 1 NOT ALLOWED

0 0 ... 0 0 0 1 0 NOT ALLOWED

. . ... . . . . . ...

0 0 ... 0 1 0 1 0 NOT ALLOWED

0 0 ... 0 1 0 1 1 75

0 0 ... 0 1 1 0 0 76

. . ... . . . . . ...

1 1 ... 1 1 1 0 1 4093

1 1 ... 1 1 1 1 0 4094

1 1 ... 1 1 1 1 1 4095

F24 F23 .......... F14 F13 (FRAC)*

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 4092

1 1 .......... 0 1 4093

1 1 .......... 1 0 4094

1 1 ......... 1 1 4095

*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN

REGISTER R5, AND THE 13-BIT LSB REGISTER STORED IN

REGISTER R6. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2

13

.

INTEGER WORD

FRAC MSB WORD

13336-024

ADF5901 Data Sheet

Rev. A | Page 20 of 26

12-Bit Integer Value (INT)

These 12 bits (Bits[DB28:DB17]) set the INT value, which

determines the integer part of the RF division factor. This INT

value is used in Equation 5. See the RF Synthesis: a Worked

Example section for more information. All integer values from

75 to 4095 are allowed.

12-Bit MSB Fractional Value (FRAC)

These 12 bits (Bits[DB16:DB5]), together with Bits[DB17:DB5]

(FRAC LSB word) in Register R6, control what is loaded as the

FRAC value into the fractional interpolator. This FRAC value

partially determines the overall RF division factor. It is also used

in Equation 1. These 12 bits are the most significant bits (MSB)

of the 25-bit FRAC value, and Bits[DB17:DB5] (FRAC LSB

word) in Register R6 are the least significant bits (LSB). See the

RF Synthesis: a Worked Example section for more information.

REGISTER 6

Control Bits

With Bits[C5:C1] set to 00110, Register R6 is programmed.

Figure 25 shows the input data format for programming

this register.

13-Bit LSB FRAC Value

These 13 bits (Bits[DB17:DB5]), together with Bits[DB16:DB5]

(FRAC MSB word) in Register R5, control what is loaded as the

FRAC value into the fractional interpolator. This FRAC value

partially determines the overall RF division factor. It is also used

in Equation 1. These 13 bits are the least significant bits (LSB)

of the 25-bit FRAC value, and Bits[DB14:DB3] (FRAC MSB

word) in Register R5 are the most significant bits (MSB). See

the RF Synthesis: a Worked Example section for more

information.

Figure 25. Register 6 (R6)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 0 0 0 0

0

F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 C4(0) C3(1) C2(1) C1(0)

CONTROL

BITS

FRAC LSB WORD

C5(0)

F12 F11 .......... F1 F0 (FRAC)*

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 8188

1 1 .......... 0 1 8189

1 1 .......... 1 0 8190

1 1 ......... 1 1 8191

1

DBR = DOUBLE-BUFFERED REGISTER.

*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN

REGISTER R5, AND THE 13-BIT LSB REGISTER STORED IN

REGISTER R6. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2

13

.

FRAC LSB WORD

DBR

1

RESERVED

13336-025

ADF5901ACPZ

ADF5901ACPZ

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