Data Sheet ADF5901
Rev. A | Page 15 of 26
Figure 19. Register 0 (R0)
REGISTER 0
Control Bits
With Bits[C5:C1] set to 00000, Register R0 is programmed.
Figure 19 shows the input data format for programming this
register.
Auxiliary Buffer Gain
Bits[DB23:DB21] set the auxiliary output buffer gain (see
Figure 19).
Auxiliary Divide by 2
Bit DB20 selects the auxiliary output divider. Setting this bit to 0
selects divide by 2 (6 GHz output). Setting the bit to 1 selects
divide by 1 (12 GHz output).
Power-Up R Counter
Bit DB15 provides the power-up bit for the R counter block.
Setting this bit to 0 performs a power-down of the counter block.
Setting this bit to 1 returns the counter block to normal
operation.
Power-Up N Counter
Bit DB14 provides the power-up bit for the N counter block.
Setting this bit to 0 performs a power-down of the counter
block. Setting this bit to 1 returns the counter block to normal
operation.
Tx2 Amplitude Calibration
Bit DB12 provides the control bit for amplitude calibration of
the Transmitter 2 (Tx2) output. Set this bit to 0 for normal
operation. Setting this bit to 1 performs an amplitude
calibration of the Tx2 output.
Tx1 Amplitude Calibration
Bit DB11 provides the control bit for amplitude calibration of
the Tx1 output. Set this bit to 0 for normal operation. Setting
this bit to 1 performs an amplitude calibration of the Tx1
output.
Power-Up VCO
Bit DB10 provides the power-up bit for the VCO. Setting this bit
to 0 performs a power-down of the VCO. Setting this bit to 1
performs a power-up of the VCO.
VCO Calibration
Bit DB9 provides the control bit for frequency calibration of the
VCO. Set this bit to 0 for normal operation. Setting this bit to 1
performs a VCO frequency and amplitude calibration.
DB31
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0 0 0 0 0 0 0
CONTROL
BITS
AG2 AG1 AG0 AD 1 1 1 1
PRC PNC 1 Tx2C Tx1C PVCO
VCAL
PADC
PTx2 PTx1 PLO
C4(0) C3(0) C2(0) C1(0)
C5(0)
PUP LO
PUP Tx1
PUP Tx2
PUP ADC
VCO CAL
PUP VCO
Tx1 AMP CAL
Tx2 AMP CAL
PUP NCNTR
PUP RCNTR
AUX DIV
RESERVED
AUX BUFFER
GAIN
PLO
0
1
PUP LO
POWER UP LO
POWER DOWN LO
PTx1
0
1
PUP Tx1
POWER UP Tx1
POWER DOWN Tx1
PTx2
0
1
PUP Tx2
POWER UP Tx2
POWER DOWN Tx2
PADC
0
1
PUP ADC
POWER UP ADC
POWER DOWN ADC
VCAL
0
1
VCO CAL
VCO FULL CAL
NORMAL OPERATION
PVCO
0
1
PUP VCO
POWER UP VCO
POWER DOWN VCO
Tx1C
0
1
Tx1 AMP CAL
Tx1 AMP CAL
NORMAL OPERATION
Tx2C
0
1
Tx2 AMP CAL
Tx2 AMP CAL
NORMAL OPERATION
AD
0
1
AUX DIV
DIV 1
DIV 2
PNC
0
1
PUP NCNTR
POWER UP NCNTR
POWER DOWN NCNTR
PNC
0
1
PUP RCNTR
POWER UP RCNTR
POWER DOWN RCNTR
AG2
AG1
AG0 AUX BUFFER GAIN
0 0 0 BUFFER DISABLED
0 0 1 GAIN SETTING 1
0 1 0 GAIN SETTING 2
0 1 1 GAIN SETTING 3
1 0 0 GAIN SETTING 4
1 0 1 GAIN SETTING 5
1 1 0 GAIN SETTING 6
1 1 1 GAIN SETTING 7
RESERVED
RESERVED
13336-019
ADF5901 Data Sheet
Rev. A | Page 16 of 26
Power-Up ADC
Bit DB8 provides the power-up bit for the ADC. Setting this bit to
0 performs a power-down of the ADC. Setting this bit to 1
performs a power-up of the ADC.
Power-Up Tx2 Output
Bit DB7 provides the power-up bit for the Tx2 output. Setting
this bit to 0 performs a power-down of the Tx2 output. Setting
this bit to 1 performs a power-up of the Tx2 output. Only one
Tx output can be powered up at any time, either Tx1 (DB6) or
Tx2 (DB7).
Power-Up Tx1 Output
Bit DB6 provides the power-up bit for the Tx1 output. Setting
this bit to 0 performs a power-down of the Tx1 output. Setting
this bit to 1 performs a power-up of the Tx1 output. Only one
Tx output can be powered up at any time, either Tx1 (DB6) or
Tx2 (DB7).
Power-Up LO Output
Bit DB5 provides the power-up bit for the LO output. Setting
this bit to 0 performs a power-down of the LO output. Setting
this bit to 1 performs a power-up of the LO output.
REGISTER 1
Control Bits
With Bits[C5:C1] set to 00001, Register R1 is programmed.
Figure 20 shows the input data format for programming this
register.
Tx Amplitude Calibration Reference Code
Bits[DB12:DB5] set the Tx amplitude calibration reference code
(see Figure 20) for the two Tx outputs during calibration.
Calibrate the output power on the Tx outputs from 20 dBm to
8 dBm by setting the Tx amplitude calibration reference code
(see Figure 7).
Figure 20. Register 1 (R1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6
DB5 DB4 DB3 DB2 DB1 DB0
1 1 1 1 1 1 1 1
CONTROL
BITS
1 1 1 1 0 1 0 1
1 1 1 C4(0) C3(0) C2(0) C1(1)
Tx AMP CAL REF CODE
C5(0)TAR7 TAR6 TAR5 TAR4 TAR3 TAR2 TAR1 TAR0
TAR7 TAR6 .......... TAR1 TAR0
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 252
1 1 .......... 0 1 253
1 1 .......... 1 0 254
1 1 ......... 1 1 255
Tx AMP CAL REF CODE
RESERVED
13336-020
Data Sheet ADF5901
Rev. A | Page 17 of 26
Figure 21. Register 2 (R2)
REGISTER 2
Control Bits
With Bits[C5:C1] set to 00010, Register R2 is programmed.
Figure 21 shows the input data format for programming this
register.
ADC Start
Bit DB15 starts the ADC conversion. Setting this bit to 1 starts
an ADC conversion.
ADC Average
Bits[DB14:DB13] program the ADC average, which is the
number of averages of the ADC output (see Figure 21).
ADC Clock Divider
Bits[DB12:DB5] program the clock divider, which is used as the
sampling clock for the ADC (see Figure 21). The output of the
R divider block clocks the ADC clock divider. Program a
divider value to ensure the ADC sampling clock is 1 MHz.
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0
CONTROL
BITS
0 0 0 0 0 1 0 AS AA0 AA0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C4(0) C3(0) C2(1) C1(0)
RESERVED ADC CLOCK DIVIDER
ADC
AVERAGE
ADC START
C5(0)
AC7 AC6 AC1 AC0
ADC CLOCK DIVIDER
0 0 0 1 1
0 0 1 0 2
. . . . .
. . . . .
. . . . .
1 1 0 0 124
1 1 0 1 125
1 1 1 0 126
1 1 1 1 127
.
.
.
.
.
.
.
.
.
.
AS
0
1
ADC START
START ADC CONVERSION
NORMAL OPERATION
AA1 AA0 ADC AVERAGE
0 0 1
0 1 2
1 0 3
1 1 4
13336-021

ADF5901ACPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Transmitter 24GHz Tx MMIC: VCO_PGA+ dual PA
Lifecycle:
New from this manufacturer.
Delivery:
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