Data Sheet ADF5901
Rev. A | Page 7 of 26
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 3, 6, 8,
10, 12, 13,
19
GND RF Ground. Tie all ground pins together.
2 TX
OUT
1 24 GHz Tx Output 1.
4, 5 TX_AHI Voltage Supply for the Tx Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground plane
as close as possible to this pin. TX_AHI must be the same value as AHI.
7 TX
OUT
2 24 GHz Tx Output 2.
11 LO
OUT
LO Output.
14 RF_AHI Voltage Supply for the RF Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground plane
as close as possible to this pin. RF_AHI must be the same value as AHI.
15 REF
IN
Reference Input. This pin is a CMOS input with a nominal threshold of DVDD/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 14. This input can be driven from a TTL or CMOS crystal oscillator, or it can be
ac-coupled.
16 AHI Voltage Supply for the Analog Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground
plane as close as possible to this pin.
17 DVDD Digital Power Supply. This supply may range from 3.135 V to 3.465 V. Place decoupling capacitors (0.1 μF, 1 nF,
and 10 pF) to the ground plane as close as possible to this pin. DVDD must be the same value as AHI.
18 VREG Internal 1.8 V Regulator Output. Connect a 220 nF capacitor to ground as close as possible to this pin.
20 CE Chip Enable. A logic low on this pin powers down the device. Taking the pin high powers up the device,
depending on the status of the power-down bit, PD1.
21 CLK Serial Clock Input. This serial clock input clocks in the serial data to the registers. The data is latched into the
32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
22 DATA Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This input is a high
impedance CMOS input.
23 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
16 latches with the latch selected via the control bits.
24 DOUT Serial Data Output.
25 MUXOUT Multiplexer Output. This multiplexer output allows either the scaled RF or the scaled reference frequency to be
accessed externally.
26 R
SET
Resistor Setting Pin. Connecting a 5.1 kΩ resistor between this pin and GND sets an internal current. The
nominal voltage potential at the R
SET
pin is 0.62 V.
27 AUX Auxiliary Output. The VCO/2 output or VCO/4 is available.
28
AUX
Complementary Auxiliary Output. The VCO/2 output or VCO/4 is available.
29 V
TUNE
Control Input to the VCO. This voltage determines the output.
30 VCO_AHI Voltage Supply for the VCO Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground
plane as close as possible to this pin. VCO_AHI must be the same value as AHI.
GND
NOTES
1. THE LFCS
P
HAS AN EXPOSED
P
AD
THA
T MUST BE CONNECTED
T
O GND.
TX
OUT
1
GND
TX_AHI
TX_AHI
GND
TX
OUT
2
GND
DOUT
LE
D
ATA
CLK
CE
GND
VREG
DVDD
ATEST
GND
LO
OUT
GND
GND
RF_AHI
REF
IN
AHI
C2
C1
VCO_AHI
V
TUNE
AUX
AUX
R
SET
MUXOUT
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
ADF5901
T
O
P
VIEW
(Not to Scale)
13336-004
