PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 31 of 48
NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
[1] All timing values referred to V
IH
and V
IL
levels with an input voltage swing of V
SS
to V
DD
.
[2] At f
clk
< 125 kHz, I
2
C-bus maximum transmission speed is derated.
Table 20. Dynamic characteristics
V
SS
= 0 V; V
DD
= 2.5 V to 6.0 V; V
LCD
= V
DD
−
2.5 V to V
DD
−
6.0 V; T
amb
=
−
40
°
C to +85
°
C; unless otherwise specified.
[1]
Symbol Parameter Conditions Min Typ Max Unit
Clock
f
clk
clock frequency normal mode;
V
DD
= 5 V
[2]
125 200 315 kHz
power saving mode;
V
DD
= 3.5 V
21 31 48 kHz
t
clk(H)
HIGH-level clock time 1 - - µs
t
clk(L)
LOW-level clock time 1 - - µs
t
PD(SYNC_N)
SYNC propagation delay - - 400 ns
t
SYNC_NL
SYNC LOW time 1 - - µs
t
PD(drv)
driver propagation delay with test loads;
V
LCD
= V
DD
− 5 V
--30µs
I
2
C-bus
t
BUF
bus free time between a STOP and
START condition
4.7 - - µs
t
HD;STA
hold time (repeated) START condition 4.0 - - µs
t
LOW
low period of the SCL clock 4.7 - - µs
t
HIGH
high period of the SCL clock 4.0 - - µs
t
SU;STA
set-up time for a repeated START
condition
4.7 - - µs
t
HD;DAT
data hold time 0 - - ns
t
SU;DAT
data set-up time 250 - - ns
t
r
rise time of both SDA and SCL signals - - 1.0 µs
t
f
fall time of both SDA and SCL signals - - 300 ns
t
SU;STO
set-up time for STOP condition 4.7 - - µs
