PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 40 of 48
NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
Table 22. Bonding pad description
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see
Figure 31).
Symbol Pad X (µm) Y (µm) Description
SDA 1 200 −1235 I
2
C-bus data input / output
SCL 2 400 −1235 I
2
C-bus clock input / output
SYNC 3 604 −1235 cascade synchronization input / output
CLK 4 856 −1235 external clock input / output
V
DD
5 1062 −1235 supply voltage
OSC 6 1080 −1235 oscillator select
A0 7 1080 −825 I
2
C-bus subaddress input
A1 8 1080 −625
A2 9 1080 −425
SA0 10 1080 −225 I
2
C-bus slave address bit 0 input
V
SS
11 1080 −25 logic ground
V
LCD
12 1080 347 LCD supply voltage
BP0 13 1080 547 LCD backplane output
BP2 14 1080 747
BP1 15 1080 947
BP3 16 1074 1235
S0 17 874 1235 LCD segment output
S1 18 674 1235
S2 19 474 1235
S3 20 274 1235
S4 21 −274 1235
S5 22 −474 1235
S6 23 −674 1235
S7 24 −874 1235
S8 25 −1074 1235
S9 26 −1080 765
S10 27 −1080 565
S11 28 −1080 365
S12 29 −1080 165
S13 30 −1080 −35
S14 31 −1080 −235
S15 32 −1080 −435
S16 33 −1080 −635
S17 34 −1080 −835
S18 35 −1080 −1035
S19 36 −1056 −1235
S20 37 −830 −1235
