PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 4 of 48
NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
Fig 2. Pin configuration for PCF8566
PCF8566
SDA S23
SCL S22
SYNC S21
CLK S20
V
DD
S19
OSC S18
A0 S17
A1 S16
A2 S15
SA0 S14
V
SS
S13
V
LCD
S12
BP0 S11
BP2 S10
BP1 S9
BP3 S8
S0 S7
S1 S6
S2 S5
S3 S4
001aai338
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22
21
24
23
26
25
40
39
38
37
36
35
34
33
32
31
30
29
28
27
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 5 of 48
NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
6.2 Pin description
Fig 3. Pin configuration for PCF8566U
mbh783
PCF8566U
36 37 38 39 40 54321
25 24 23 22 21 16
15
14
13
12
11
10
17181920
9
8
7
6
30
31
32
33
34
35
26
27
28
29
S23
S22
S21
S20
S19
V
DD
CLK
SYNC
SCL
SDA
S5
S7
S8
S6
SA0
A2
A1
A0
OSC
S16
S17
S18
V
SS
V
LCD
BP0
BP2
BP1
S11
S10
S9
S12
S14
S13
S15
BP3
S0
S1
S2
S3
S4
Table 3. Pin description
Symbol Pin Description
SDA 1 I
2
C-bus data input and output
SCL 2 I
2
C-bus clock input and output
SYNC 3 cascade synchronization input and output
CLK 4 external clock input and output
V
DD
5 positive supply voltage
[1]
OSC 6 oscillator select
A0 7 I
2
C-bus subaddress inputs
A1 8
A2 9
SA0 10 I
2
C-bus slave address bit 0 input
V
SS
11 logic ground
V
LCD
12 LCD supply voltage
PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 6 of 48
NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
[1] The substrate (rear side of the die) is wired to V
DD
but should not be electrically connected.
7. Functional description
The PCF8566 is a versatile peripheral device designed to interface any
microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static
or multiplexed LCD containing up to 4 backplanes and up to 24 segments.
The display configurations possible with the PCF8566 depend on the number of active
backplane outputs required. Display configuration selection is shown in Table 4. All of the
display configurations given in Table 4 can be implemented in the typical system shown in
Figure 4.
The host microprocessor or microcontroller maintains the 2-line I
2
C-bus communication
channel with the PCF8566.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to V
SS
. The only other connections required to complete the system are the
power supplies (pins V
DD
, V
SS
and V
LCD
) and the LCD panel selected for the application.
BP0 13 LCD backplane outputs
BP2 14
BP1 15
BP3 16
S0 to S23 17 to 40 LCD segment outputs
Table 3. Pin description
…continued
Symbol Pin Description
Table 4. Display configurations
Backplanes Elements 7-segment numeric 14-segment numeric Dot matrix
Digits Indicator
symbols
Characters Indicator
symbols
4 96 12 12 6 12 96 (4 × 24)
3729941672 (3× 24)
248663648 (2× 24)
1243311024

PCF8566TS/1,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers 24 SGMT 315KHz
Lifecycle:
New from this manufacturer.
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