PCF8566_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 25 February 2009 34 of 48
NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8566s. This synchronization is guaranteed after the power-on reset. The only time
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by defining a multiplex mode when PCF8566s with
differing SA0 levels are cascaded).
SYNC is organized as an input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor. A PCF8566 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCF8566 to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCF8566 are shown in Figure 27.
Fig 26. Cascaded PCF8566 configuration
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
CLK
OSC
SYNC
1
17 to 40
13 to 16
13 to 16
2
3
4
6
78
512
91011
7 8 9 10 11
24 segment drives
4 backplanes
24 segment drives
LCD PANEL
(up to 1536
elements)
PCF8566
PCF8566
A0 A1 A2 SA0
mgg384
SDA
SCL
SYNC
CLK
OSC
1
512
2
3
4
6
17 to 40
BP0 to BP3
(open-circuit)
A0 A1 A2 SA0
BP0 to BP3
V
DD
V
LCD
V
SS
V
DD
V
LCD
V
SS
V
LCD
V
DD
V
SS
R ≤
t
rise
2 C
bus
