NCP81255
www.onsemi.com
13
Differential Current Feedback Amplifier
The NCP81255 controller has a low offset, differential
amplifier to sense output inductor current. An external
low-pass filter can be used to superimpose a reconstruction
of the AC inductor current onto the DC current signal sensed
across the inductor. The low-pass filter time constant should
match the inductor L/DCR time constant by setting the filter
pole frequency equal to the zero of the output inductor. This
makes the filter AC output mimic the product of AC inductor
current and DCR, with the same gain as the filter DC output.
It is best to perform fine tuning of the filter pole during
transient testing.
F
Z
+
DCR @ 25 C
2 @ p @ L
(eq. 2)
°
(eq. 3)
F
P
+
1
2 @ p @
ǒ
R
PHSP
@
ǒ
R
TH
)R
CSSP
Ǔ
R
PHSP
)R
TH
)R
CSSP
Ǔ
@ C
CSSP
Forming the low-pass filter with an NTC thermistor (R
TH
)
placed near the output inductor, compensates both the DC
gain and the filter time constant for the inductor DCR change
with temperature. The values of R
PHSP
and R
CSSP
are set
based on the effect of temperature on both the thermistor and
inductor. The CSP and CSN pins are high impedance inputs,
but it is recommended that the low-pass filter resistance not
exceed 10 kW in order to avoid offset due to leakage current.
It is also recommended that the voltage sense element
(inductor DCR) be no less than 0.5 mW for sufficient current
accuracy. Recommended values for the external filter
components are:
R
PHSP
= 7.68 kW
R
CSSP
= 14.3 kW
R
TH
= 100 kW, Beta = 4300
(eq. 4)
C
CSSP
+
L
PHASE
R
PHSP
@
ǒ
R
TH
)R
CSSP
Ǔ
R
PHSP
)R
TH
)R
CSSP
@ DCR
Using 2 parallel capacitors in the low-pass filter allows
fine tuning of the pole frequency using commonly available
capacitor values.
The DC gain equation for the current sense amplifier
output is:
(eq. 5)
V
CURR
+
R
TH
) R
CSSP
R
PHSP
) R
TH
) R
CSSP
@ I
OUT
@ DCR
Figure 6.
R
CSSP
CSP
A
V
= 1
+
R
TH
R
PHSP
C
CSSP
CSN
To Inductor
Current
Sense AMP
CURR
COMP
RAMP PWM
PWM
Generator
t
The amplifier output signal is combined with the COMP
and RAMP signals at the PWM comparator inputs to
produce the Ramp Pulse Modulation (RPM) PWM signal.
PSYS
The PSYS pin is an analog input to the NCP81255. It is
a system input power monitor that facilitates the monitoring
of the total platform system power. For more details about
PSYS please contact Intel, Inc.
NCP81255
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14
Load-line Programming (DROOP)
An output load-line is a power supply characteristic
wherein the regulated (DC) output voltage decreases by
a voltage V
DROOP
, proportional to load current. This
characteristic can reduce the output capacitance required to
maintain output voltage within limits during load transients
faster than those to which the regulation loop can respond.
In the NCP81255, a load-line is produced by adding a signal
proportional to output load current (V
DROOP
) to the output
voltage feedback signal – thereby satisfying the voltage
regulator at an output voltage reduced proportional to load
current. V
DROOP
is developed across a resistance between
the VSP pin and the output voltage sense point.
Figure 7.
VSN
VSP
VSN
VSP
+
+
gm
S
R
CSSP
CSP
A
V
= 1
+
R
TH
R
PHSP
C
CSSP
CSN
To Inductor
Current
Sense AMP
t
C
SNSSP
R
DRPSP
R
DRPSP
C
DRPSP
To VCC_SENSE
V
DROOP
+ R
DRPSP
@ gm @
R
TH
) R
CSSP
R
PHSP
) R
TH
) R
CSSP
@ I
OUT
@ DCR
(eq. 6)
The loadl-ine is programmed by choosing R
DRPSP
such
that the ratio of voltage produced across R
DRPSP
to output
current is equal to the desired load-line.
(eq. 7)
R
DRPSP
+
Loadline
gm @ DCR
@
R
PHSP
) R
TH
) R
CSSP
R
TH
) R
CSSP
I
CC
Max
A resistor to ground on the IMAX pin programs these
registers at the time the part is enabled. 10 mA is sourced
from these pins to generate a voltage on the program resistor.
The resistor value should be no less than 10 kW.
(eq. 8)
ICC_MAX
21h
+
R @ 10 mA @ 255 A
2V
NCP81255
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15
Programming IOUT
The IOUT pin sources a current in proportion to the
ILIMIT sink current. The voltage on the IOUT pin is
monitored by the internal A/D converter and should be
scaled with an external resistor to ground such that a load
equal to ICC_MAX generates a 2 V signal on IOUT.
A pull-up resistor from 5 V VCC can be used to offset the
IOUT signal positive if needed.
Figure 8.
R
CSSP
CSP
A
V
= 1
+
R
TH
R
PHSP
C
CSSP
CSN
To Inductor
Current
Sense AMP
t
Current
Monitor
R
IOUTSP
gm
IOUT
IOUT
(eq. 9)
R
IOUTSP
+
2V
gm @
R
TH
)R
CSSP
R
PHSP
)R
TH
)R
CSSP
@ IccMax @ DCR
Programming the DAC Feed-Forward Filter
The NCP81255 outputs a pulse of current from the VSN
pin upon each increment of the internal DAC following
a DVID UP command. A parallel RC network inserted into
the path from VSN to the output voltage return sense point,
VSS_SENSE, causes these current pulses to temporarily
decrease the voltage between VSP and VSN. This causes the
output voltage during DVID to be regulated slightly higher,
in order to compensate for the response of the Droop
function to the inductor current flowing into the charging
output capacitors. RFFSP sets the gain of the DAC
feed-forward and CFFSP provides the time constant to
cancel the time constant of the system per the following
equations. C
OUT
is the total output capacitance of the
system.
Figure 9.
VSN
VSP
VSN
VSP
+
+
S
C
SNSSP
R
FFSP
C
FFSP
To VCC_SENSE
DAC
Feed-Forward
DAC
gm
DAC Feed-Forward Current
From Intel
proprietary
interface
Interface
DAC
(eq. 10)
R
FFSP
+
Loadline @ C
OUT
1.35 @ 10
*9
(W)
C
FFSP
+
200
R
FFSP
(nF)

NCP81255MNTXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG CTRLR IMVP8 1OUT 40QFN
Lifecycle:
New from this manufacturer.
Delivery:
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