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NCP81255MNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
NCP81255
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4
Figure 3. Pin Configuration
1
2
3
4
5
6
7
8
9
10
VR_HOT#
SDIO
ALERT
SCLK
PGND
VR_RDY
VIN
BST
GH
SW
11
12
13
14
15
16
17
18
19
20
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
PGND
DOSC/ADDR/VBOOT
TSENSE
IMAC
PVCC
PGND
GL
GL
SW
30
29
28
27
26
25
24
21
SW
22
SW
23
EN
VCC
IOUT
CSP
CSN
ILIM
COMP
VSN
VSP
PSYS
40
39
38
37
36
35
34
33
32
31
41 GND
42
VIN
43
PGND
44
GL
NCP81255
Table 1. NCP81255 PIN DESCRIPTIONS
Pin No.
Symbol Description
1 VR_HOT# Thermal Logic Output for Over-Temperature Condition on either TSENSE
2 SDIO Serial VID Data Interface
3 ALERT# Serial VID ALERT#
4 SCLK Serial VID Clock
5 PGND Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
6 VR_RDY VR_RDY Indicates the Controller is Ready to Accept Intel proprietary interface Commands
7 VIN
Input Voltage for HS FET Drain. 22 mF or More Ceramic Caps must Bypass this Input to Power
Ground. Place Close to Pins
8 BST Provides Bootstrap Voltage for the HS Gate Driver. A Cap is Required from this Pin to SW
9 GH Gate of HS FET
10 SW Switching Node. Provides a Return Path for the Integrated HS Driver. Internally Connected to the
Source of the HS FET
11 VIN
Input Voltage for HS FET Drain. 22 mF or More Ceramic Caps must Bypass this Input to Power
Ground. Place Close to Pins
12 VIN
Input Voltage for HS FET Drain. 22 mF or More Ceramic Caps must Bypass this Input to Power
Ground. Place Close to Pins
13 VIN
Input Voltage for HS FET Drain. 22 mF or More Ceramic Caps must Bypass this Input to Power
Ground. Place Close to Pins
14 VIN
Input Voltage for HS FET Drain. 22 mF or More Ceramic Caps must Bypass this Input to Power
Ground. Place Close to Pins
15 PGND Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
16 PGND Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
17 PGND Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
18 PGND Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
NCP81255
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5
Table 1. NCP81255 PIN DESCRIPTIONS (continued)
Pin No. DescriptionSymbol
19 PGND Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
20 PGND Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
21 SW Switch Node. Pins to be Connected to an External Inductor. These Pins are Interconnection
between Internal HS and LS FETs
22 SW Switch Node. Pins to be Connected to an External Inductor. These Pins are Interconnection
between Internal HS and LS FETs
23 SW Switch Node. Pins to be Connected to an External Inductor. These Pins are Interconnection
between Internal HS and LS FETs
24 GL Gate of LS FET
25 GL Gate of LS FET
26 PGND Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET
27 PVCC
Voltage Supply of Gate Drivers. A 4.7 mF or Larger Ceramic Capacitor Bypasses this Input to GND,
Placed as Close to the Pin as Possible
28 IMAX ICCMAX Register Program
29 TSENSE External Temperature Sense Network is Connected to this Pin
30 DOSC/ADDR/
VBOOT
Programming for F
SW
, Intel proprietary interface Address, and V
BOOT
. A Resistor to GND Programs
these Values during Start-up, per Look-up Table
31 PSYS System Power Signal Input. A Resistor to Ground Scales this Signal
32 VSP Differential Output Voltage Sense Positive
33 VSN Differential Output Voltage Sense Negative
34 COMP Compensation
35 ILIM Current-Limit Program
36 CSN Differential Current Sense Negative
37 CSP Differential Current Sense Positive
38 IOUT IOUT Gain Program
39 VCC
Power Supply Input Pin of Control Circuits. A 1 mF or Larger Ceramic Capacitor Bypasses this Input
to Ground, Placed Close to the Controller
40 EN Enable
41 GND Flag. Analog Ground. Ground of Internal Control Circuits
42 VIN
Flag. Input Voltage for HS FET Drain. 22 mF or More Ceramic Caps must Bypass this Input to
Power Ground. Place Close to Pins
43 PGND Flag. Power Ground. Power Supply Ground Pins, Connected to Source of Internal LS FET.
44 GL Flag. Gate of LS FET
NCP81255
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6
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol Min Max Unit
Power Supply Voltage to PGND V
VIN
− 30 V
Switch Node to PGND V
SW
−0.3 30 V
Analog Supply Voltage to GND V
CC
, V
CCP
−0.3 6.5 V
BST to PGND BST_PGND −0.3 33
38 (< 50 ns)
V
BST to SW BST_SW −0.3 6.5 V
GH to SW GH −0.3
−2 (< 200 ns)
BST + 0.3 V
GL to GND GL −0.3
−2 (< 200 ns)
V
CCP
+ 0.3 V
VSN to GND VSN −0.3 0.3 V
IOUT IOUT −0.3 2.5 V
PGND to GND PGND −0.3 0.3 V
Other Pins −0.3 V
CC
+ 0.3 V
Latch Up Current: (Note 1)
All Pins, Except Digital Pins
Digital Pins
I
LU
−100
−10
100
10
mA
Operating Junction Temperature Range T
J
−40 125 °C
Operating Ambient Temperature Range T
A
−40 100 °C
Storage Temperature Range T
STG
−40 150 °C
Thermal Resistance Junction to Board (Note 2)
R
q
JB
8.2 °C/W
Thermal Resistance Junction to Ambient (Note 2)
R
q
JA
21.8 °C/W
Power Dissipation at T
A
= 25°C (Note 3) P
D
4.59 W
Moisture Sensitivity Level (Note 4) MSL 3 −
ESD Human Body Model HBM 2,000 V
ESD Machine Model MM 200 V
ESD Charged Device Model CDM 1,000 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Latch up Current per JEDEC standard: JESD78 Class II.
2. The thermal resistance values are dependent on the internal losses split between devices and the PCB heat dissipation. This data is based
on a typical operation condition with a 4-layer FR−4 PCB board, which as two, 1-ounce copper internal power and ground planes and 2-ounce
copper traces on top and bottom layers with approximately 80% copper coverage. No airflow and no heat sink applied (reference
EIA/JEDEC 51.7). It also does not account for other heat sources that may be present on the PCB next to the device in question (such as
inductors, resistors, etc.)
3. The maximum power dissipation (PD) is dependent on input voltage, output voltage, output current, external components selected, and PCB
layout. The reference data is obtained based on T
JMAX
= 125°C and R
q
JA
= 21.8°C/W.
4. Moisture Sensitivity Level (MSL): 3 per IPC/JEDEC Standard: J−STD−020D.1.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

NCP81255MNTXG

Mfr. #:
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Manufacturer:
ON Semiconductor
Description:
IC REG CTRLR IMVP8 1OUT 40QFN
Lifecycle:
New from this manufacturer.
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