NCP81255
www.onsemi.com
17
Ultrasonic Mode
The switching frequency of a rail in DCM will decrease
at very light loads. Ultrasonic Mode forces the switching
frequency to stay above the audible range.
Input Under-Voltage Protection
The controller is protected against under-voltage on the
VCC, VCCP, and VFF pins.
Under-Voltage Protection
Under-voltage protection will shut off the output similar
to OCP to protect against short circuits. The threshold is
specified in the parametric spec tables and is not adjustable.
Over-Current Protection (OCP)
A programmable current limit is programmed with
a resistor between the ILIM pin and ground. to this resistor
is compared to the ILIM Threshold Voltage (V
CL
). If the
ILIM pin voltage exceeds the lower Threshold Voltage, an
internal latch-off timer starts. When the timer expires, the
controller shuts down if the fault is not removed. If the
voltage at the ILIM pin exceeds the higher Threshold
Voltage, the controller shuts down immediately. To recover
from an OCP fault, the EN pin or V
CC
voltage must be
cycled low.
Layout Notes
The NCP81255 has differential voltage and current
monitoring. This improves signal integrity and reduces
noise issues related to layout for easy design use. To insure
proper function there are some general rules to follow.
Always place the inductor current sense RC filters as close
to the CSN and CSP pins on the controller as possible. Place
the VCC decoupling caps as close as possible to the
controller VCC pin.
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
• Power Paths: Use wide and short traces for power
paths (such as VIN, VOUT, SW, and PGND) to reduce
parasitic inductance and high-frequency loop area. It is
also good for efficiency improvement.
• Power Supply Decoupling: The device should be well
decoupled by input capacitors and input loop area
should be a small as possible to reduce parasitic
inductance, input voltage spike, and noise emission.
Usually, a small low-ESL MLCC is placed very close
to VIN and PGND pins.
• VCC Decoupling: Place decoupling caps as close as
possible to the controller VCC and VCCP pins.
The filter resistor at VCC pin should be not higher than
2.2 W to prevent large voltage drop.
• Switching Node: SW node should be a copper pour, but
compact because it is also a noise source.
• Bootstrap: The bootstrap cap and an optional resistor
need to be very close and directly connected between
BST and SW pins. No need to externally connect pin 10
to SW node because it has been internally connected to
other SW pins.
• Ground: It would be good to have separated ground
planes for PGND and GND and connect the two planes
at one point. Directly connect GND pin to the exposed
panda then connect to GND ground plane through vias.
• Voltage Sense: Use Kelvin sense pair and arrange
a “quiet” path for the differential output voltage sense.
• Current sense: Careful layout for current sensing is
critical for jitter minimization, accurate current
limiting, and IOUT reporting. The temperature
compensating thermistor should be placed as close as
possible to the inductor. The wiring path should be kept
as short as possible and well away from the switch
node.
• Intel proprietary interface Bus: The Serial VID bus is a
high-speed data bus and the bus routing should be done
to limit noise coupling from the switching node. The
signals should be routed with the Alert# line in between
the Intel proprietary interface clock and Intel
proprietary interface data lines. The Intel proprietary
interface lines must be ground referenced and each
line’s width and spacing should be such that they have
nominal 50 W impedance with the board stack-up.
Thermal Layout Considerations
Good thermal layout helps high power dissipation from
a small package with reduced temperature rise. Thermal
layout guidelines are:
• The exposed pads must be well soldered on the board.
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More free vias are welcome to be around IC and
underneath the exposed pads to connect the inner
ground layers to reduce thermal impedance.
• Use large area copper pour to help thermal conduction
and radiation.
• Do not put the inductor to be too close to the IC, thus
the heat sources are distributed.
