MKS22FN128VFT12 Datasheet MKS20FN256VFT12, MKS22FN256VFT12, MKS22FN128VFT12 | P10-P12

Block diagram

KS22 Product Brief, Rev. 2, 03/2016

10 Freescale Semiconductor, Inc.

• Supports the generation of hardware triggers when the counter overflows (per channel)

3.1.6.3. Periodic Interrupt Timers (PITs)

• Up to four general-purpose interrupt timers

• Up to four interrupt timers for triggering of ADC conversions

• 32-bit counter resolution

• Clocked by the bus clock

• DMA support

• Two timers can be cascaded to form a 64-bit timer

3.1.6.4. Low-Power Timer

• Operates as timer or pulse counter

• Selectable clock for prescaler / glitch filter

• Configurable glitch filter or prescaler

• Interrupt generated on timer compare

• Hardware trigger generated on timer compare

3.1.6.5. Real-Time Clock (RTC)

• Independent power supply, POR, and 32 kHz crystal oscillator

• 32-bit second counter with 32-bit alarm

• 16-bit prescaler with compensation

• Register write protection

— Hard lock requires VBAT POR to enable write access

— Soft lock requires system reset to enable write/read access

3.1.7. Communication interface

3.1.7.1. USB On-The-Go Module (FS/LS)

• Complies with USB specification rev 2.0

• USB host mode

— Supports Enhanced-Host-Controller Interface (EHCI)

— Enables direct connection of FS/LS devices without OHCI/UHCI companion controller

— Supported by Linux and other commercially available operating systems

• USB device mode

— Full-speed operation via the on-chip transceiver

— Supports one upstream-facing port

Block diagram

KS22 Product Brief, Rev. 2, 03/2016

Freescale Semiconductor, Inc. 11

— Supports 16 programmable bidirectional USB endpoints, including endpoint 0

• Suspend mode/low power

— As a host, firmware can suspend individual devices or entire USB, and disable chip

clocks for low-power operation

— Device supports low-power suspend

— Remote wakeup supported for host and device

— Integrated with the processor’s low-power modes

• Includes on-chip full-speed (12 Mbps) and low-speed (1.5 Mbps) transceivers

• A configurable connection, enabling any UART transmit and receive pins to be connected to the

full-speed USB physical layer

3.1.7.2. Serial Peripheral Interface (SPI)

• Full-duplex three-wire synchronous transfers

• Master mode or Slave mode

• Data streaming operation in Slave mode with continuous slave selection

• Buffered transmit/receive operation using the Transmit/Receive First-In First-Out (TX/RX

FIFO) with a depth of four entries

• Programmable transfer attributes on a per-frame basis

• Multiple Peripheral Chip Select (PCS) (six PCS are available for SPI0 and four PCS for SPI1),

expandable to 64 with external demultiplexer

• Deglitching support for up to 32 Peripheral Chip Selects (PCSes) with external demultiplexer

• DMA support for adding entries to TX FIFO, and removing entries from RX FIFO

• Global interrupt request line

• Modified SPI transfer formats for communication with slower peripheral devices

• Power-saving architectural features

3.1.7.3. Low-Power Inter-Integrated Circuit (LPI

• Standard, Fast, Fast+, and Ultra Fast modes are supported

• HS mode supported in Slave mode

• Multi-master support including synchronization and arbitration

• Clock stretching

• General-call, 7-bit, and 10-bit addressing

• Software reset, START byte, and Device ID require software support

Block diagram

KS22 Product Brief, Rev. 2, 03/2016

12 Freescale Semiconductor, Inc.

3.1.7.4. UART

• Full-duplex operation

• 13-bit baud rate selection with /32 fractional divide, based on the module clock frequency

• Programmable 8-bit or 9-bit data formats

• Programmable transmitter output polarity

• Programmable receive input polarity

• Up to 14-bit break character transmission

• 11-bit break character detection option

• Two receiver wakeup methods with idle line or address mark wakeup

• Address match feature in the receiver to reduce address mark wakeup ISR overhead

• Ability to select MSB or LSB to be the first bit on wire

• UART0 supporting ISO-7816 protocol to interface with SIM cards and smart cards

• Receiver framing error detection

• Hardware parity generation and checking

• 1/16 bit-time noise detection

• DMA interface

3.1.7.5. LPUART

• Full-duplex, standard Non-Return-to-Zero (NRZ) format

• Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4×

to 32×

• Transmit and receive baud rate can operate asynchronously to the bus clock:

— Baud rate can be configured independently of the bus clock frequency

— Supports operation in Stop modes

• Interrupt, DMA, or polled operation:

• Hardware parity generation and checking

• Programmable 8-bit, 9-bit, or 10-bit character length

• Programmable 1-bit or 2-bit stop bits

• Three receiver wakeup methods:

— Idle line wakeup

— Address mark wakeup

— Receive data match

• Automatic address matching to reduce ISR overhead:

— Address mark matching

— Idle line address matching

— Address match start, address match end

• Optional 13-bit break character generation/11-bit break character detection

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MKS22FN128VFT12

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Description:

ARM Microcontrollers - MCU MKS22FN128VFT12/HVQFN48///TRAY MULTIPLE DP BAKEABL

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MKS22FN128VFT12

MKS22FN128VFT12

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