MKS22FN128VFT12 Datasheet MKS20FN256VFT12, MKS22FN256VFT12, MKS22FN128VFT12 | P4-P6

Block diagram

KS22 Product Brief, Rev. 2, 03/2016

4 Freescale Semiconductor, Inc.

• Three-stage pipeline with branch speculation

• Integrated bus matrix

• Integrated Digital Signal Processor (DSP)

• Configurable Nested Vectored Interrupt Controller (NVIC)

• Advanced configurable debug component

• Single-Precision Floating-Point Unit (SPFPU)

3.1.1.2. Nested Vectored Interrupt Controller (NVIC)

• Close coupling with Cortex-M4 core's Harvard architecture enables low-latency interrupt

handling

• Up to 120 interrupt sources

• Includes a single non-maskable interrupt

• 16 levels of priority, with each interrupt source being dynamically configurable

• Supports nesting of interrupts when higher-priority interrupts are activated

• Relocatable vector table

3.1.1.3. Wakeup Interrupt Controller (WIC)

• Supports interrupt handling when system clocking is disabled in low-power modes

• Takes over and emulates the NVIC behavior when correctly primed by the NVIC on entering

deep sleep

• A rudimentary interrupt-masking system with no prioritization logic signals for wakeup as soon

as non-masked interrupt is detected

• Does not contain programmer’s model visible state, and is therefore invisible to end users, other

than through the benefits of reduced power consumption while sleeping

3.1.1.4. Debug controller

• Serial-Wire JTAG Debug Port (SWJ-DP) combines

— External interface that provides a standard JTAG or cJTAG interface for debug access

— External interface that provides a serial-wire bidirectional debug interface

• Debug Watchpoint and Trace (DWT) with the following functionality:

— Four comparators configurable as hardware watchpoint, PC sampler event trigger, or data

address sampler event trigger

— Several counters or data match event trigger for performance profiling

— Configurable to emit PC samples at defined intervals, or to emit interrupt event

information

• Instrumentation Trace Macrocell (ITM) with the following functionality:

— Software trace—writing directly to ITM stimulus registers can cause packet emitting

Block diagram

KS22 Product Brief, Rev. 2, 03/2016

Freescale Semiconductor, Inc. 5

— Hardware trace—packets generated by DWT are emitted by ITM

— Time stamping—emitted relative to packets

• Test Port Interface Unit (TPIU) acts as a bridge between ITM and off-chip Trace Port Analyzer

• Flash Patch and Breakpoints (FPB) implements hardware breakpoints, and patches code and data

from code space to system space

3.1.2. System modules

3.1.2.1. Power Management Control Unit (PMC)

• Separate digital (regulated) and analog (referenced to digital) supply outputs

• Programmable power-saving modes

• No output supply decoupling capacitors required

• Available wakeup from power-saving modes via RTC and external inputs

• Integrated Power-On Reset (POR)

• Integrated Low Voltage Detect (LVD) with reset (brownout) capability

• Selectable LVD trip points

• Programmable Low Voltage Warning (LVW) interrupt capability

• Buffered bandgap reference voltage output

• Factory-programmed trim for bandgap and LVD

• 1 kHz Low-Power Oscillator (LPO)

3.1.2.2. DMA Channel Multiplexer (DMA MUX)

• Up to 16 independently selectable DMA channel routers

• Four periodic trigger sources available

• Each channel router can be assigned to one of 63 possible peripheral DMA sources

3.1.2.3. DMA controller

• Up to 16 fully programmable channels with 32-byte transfer control descriptors

• Data movement via dual-address transfers for 8-bit, 16-bit, 32-bit, 128-bit, and 256-bit data

values

• Programmable source and destination addresses, transfer size, and support for enhanced address

modes

• Support for major and minor nested counters with one request and one interrupt per channel

• Support for channel-to-channel linking and scatter/gather for continuous transfers with

fixed-priority and round-robin channel arbitration

Block diagram

KS22 Product Brief, Rev. 2, 03/2016

6 Freescale Semiconductor, Inc.

3.1.2.4. System clocks

• Frequency-Locked Loop (FLL)

— Digitally-Controlled Oscillator (DCO) with programmable frequency range

— Internal or external reference clock can be used to control the FLL

— 0.2% resolution using 32 kHz internal reference clock

• Phase-Locked Loop (PLL)

— Voltage-Controlled Oscillator (VCO)

— External reference clock is used to control the PLL

— Modulo VCO frequency divider phase/frequency detector

— Integrated loop filter

• Internal reference clock generator

— Can be used to control the FLL

— Either slow or fast clock can be selected as the clock source for the MCU

— Can be used as a clock source for other on-chip peripherals

• External clock from the Crystal Oscillator

— Can be used to control the FLL and/or the PLL

— Can be selected as the clock source for the MCU

• External clock monitor with reset request capability

• Lock detector with interrupt request capability for use with the PLL

• Auto Trim Machine (ATM) for trimming both slow and fast internal reference clocks

• Multiple clock source options available for most peripherals

3.1.3. Memories and memory interfaces

3.1.3.1. On-chip memory

• Up to 256 KB program Flash memory

• 64 KB SRAM

• Security circuitry to prevent unauthorized access to RAM and Flash contents

3.1.4. Security and integrity

3.1.4.1. Cyclic Redundancy Check (CRC)

• Hardware CRC generator circuit using 16-bit/32-bit shift register

• User-configurable 16-bit/32-bit CRC

• Programmable generator polynomial

• Error detection for all single-bit, double-bit, odd-bit, and most multi-bit errors

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MKS22FN128VFT12

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ARM Microcontrollers - MCU MKS22FN128VFT12/HVQFN48///TRAY MULTIPLE DP BAKEABL

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MKS22FN128VFT12

MKS22FN128VFT12

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