MKS22FN128VFT12 Datasheet MKS20FN256VFT12, MKS22FN256VFT12, MKS22FN128VFT12 | P7-P9

Block diagram

KS22 Product Brief, Rev. 2, 03/2016

Freescale Semiconductor, Inc. 7

• Programmable initial seed value

• High-speed CRC calculation

• Optional feature to transpose input data and CRC result via transpose register, required on

applications where bytes are in the LSB format

3.1.4.2. Watchdog Timer (WDOG)

• Independent, configurable clock source input

• Write-once control bits with unlock sequence

• Programmable timeout period

• Ability to test the Watchdog Timer and reset

• Windowed refresh option

• Robust refresh mechanism

• Cumulative count of Watchdog resets between Power-On Resets

• Configurable interrupt on timeout

3.1.4.3. External Watchdog Monitor (EWM)

• Independent 1 kHz LPO clock source

• Output signal to gate external circuit, which is controlled by CPU service or external input

3.1.4.4. Random Number Generator Accelerator (RNGA)

• Supports the key-generation algorithm defined in the Digital Signature Standard

— http://www.itl.nist.gov/fipspubs/fip186.htm

• Integrated entropy sources capable of providing the PRNG with entropy for its seed

3.1.5. Analog modules

3.1.5.1. 16-bit Analog-to-Digital Converter (ADC)

• Linear successive approximation algorithm with up to 16-bit resolution

• Output modes:

— Differential 16-bit, 13-bit, 11-bit, and 9-bit modes, in two’s complement 16-bit

sign-extended format

— Single-ended 16-bit, 12-bit, 10-bit, and 8-bit modes, in right-justified unsigned format

• Single or continuous conversion

• Configurable sample time and conversion speed/power

• Conversion complete and hardware average complete flag and interrupt

• Input clock selectable from up to four sources

Block diagram

KS22 Product Brief, Rev. 2, 03/2016

8 Freescale Semiconductor, Inc.

• Operation in low-power modes for low noise

• Asynchronous clock source for low-noise operation with an option to output the clock

• Selectable asynchronous hardware conversion trigger with hardware channel select

• Automatic compare with interrupt for various programmable values

• Temperature sensor

• Hardware average function

• Self-calibration mode

3.1.5.2. High-Speed Analog Comparator (CMP)

• 6-bit DAC programmable reference generator output

• Up to seven selectable comparator inputs; each input can be compared with any input by any

polarity sequence

• Selectable interrupt on rising edge, falling edge, or either rising or falling edges of the

comparator output

• Comparator output supports:

— Sampled

— Windowed (ideal for certain PWM zero-crossing-detection applications)

— Digitally filtered using external sample signal or scaled peripheral clock

• Two performance modes:

— Shorter propagation delay at the expense of higher power

— Low power, with longer propagation delay

• Operational in all MCU power modes

3.1.5.3. 12-bit Digital-to-Analog Converter (DAC)

• 12-bit resolution

• On-chip programmable reference generator output. The voltage output range is from 1/4096 V

to V

, and the step is 1/4096 V

, where V

is the input voltage

• V

can be selected from one reference source

• Static operation in Normal Stop mode

• 16-word data buffer supported with multiple operation modes

• DMA support

Block diagram

KS22 Product Brief, Rev. 2, 03/2016

Freescale Semiconductor, Inc. 9

3.1.6. Timers

3.1.6.1. Programmable Delay Block (PDB)

• Up to 15 trigger input sources and software trigger sources

• One configurable PDB channel for ADC hardware trigger

— One trigger output for ADC hardware trigger, and up to two pre-trigger outputs for ADC

trigger select per PDB channel

— One 16-bit delay register per pre-trigger output

— Optional bypass of the pre-trigger outputs’ delay registers

— Operation in One-Shot or Continuous modes

— Optional Back-To-Back mode operation, which enables the ADC conversions completely

to trigger the next PDB channel

• One DAC interval trigger

— One interval trigger output for DAC

— One 16-bit delay interval register

— Optional bypass of the delay interval trigger registers

— Optional external triggers

• Up to eight pulse outputs (pulse-outs)

— Pulse-outs can be enabled or disabled independently

— Programmable pulse width

• DMA support

3.1.6.2. LPTPM

• TPM clock mode is selectable

— It can increment on every edge of the asynchronous counter clock

— It can increment on the rising edge of an external clock input synchronized to the

asynchronous counter clock

• Prescaler can divide by 1, 2, 4, 8, 16, 32, 64, or 128

• TPM includes a 16-bit counter

— It can be a free-running counter or a modulo counter

— The counting can be either up or up-down

• Includes six channels that can be configured for input capture, output compare, edge-aligned

PWM mode, or center-aligned PWM mode

• Supports the generation of interrupt and/or DMA requests when the counter overflows

(per channel)

• Supports selectable trigger input to reset the counter, or to make it start incrementing

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MKS22FN128VFT12

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ARM Microcontrollers - MCU MKS22FN128VFT12/HVQFN48///TRAY MULTIPLE DP BAKEABL

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MKS22FN128VFT12

MKS22FN128VFT12

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