AD7943/AD7945/AD7948
REV. B–10–
AD7948 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
I
OUT1
DAC current output terminal 1. Normally terminated at the virtual ground of output amplifier.
AGND Analog Ground Pin. This pin connects to the back gates of the current steering switches. The DAC I
OUT2
terminal is also connected internally to this point.
DGND Digital Ground Pin.
CSMSB Chip Select Most Significant Byte. Active Low Input. Used in combination with WR to load external data into
the input register or in combination with LDAC and WR to load external data into both input and DAC registers.
DF/DOR Data Format/Data Override. When this input is low, data in the DAC register is forced to one of two override
codes selected by CTRL. When the override signal is removed, the DAC output returns to reflect the value in
the DAC register. With DF/DOR high, CTRL selects either a left or right justified input data format. For normal
operation, DF/DOR is held high. See Table I.
CTRL Control Input. See DF/DOR description.
DB7–DB0 Digital Data Inputs.
LDAC Load DAC input, active low. This signal, in combination with others, is used to load the DAC register from
either the input register or the external data bus.
CSLSB Chip Select Least Significant (LS) Byte. Active Low Input. Used in combination with WR to load external data
into the input register or in combination with WR and LDAC to load external data into both input and DAC
registers.
WR Write input, active low. This active low signal, in combination with others is used in loading external data into
the AD7948 input register and in transferring data from the input register to the DAC register.
V
DD
Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode
Operation.
V
REF
DAC reference input.
R
FB
DAC feedback resistor pin.
Table II. Truth Table for AD7948 Write Operation
WR CSMSB CSLSB LDAC Function
0 1 0 1 Load LS Byte to Input Register
0 1 0 0 Load LS Byte to Input Register and DAC Register
0 0 1 1 Load MS Byte to Input Register
0 0 1 0 Load MS Byte to Input Register and DAC Register
0 1 1 0 Load Input Register to DAC Register
1 X X X No Data Transfer
Table I. Truth Table for DF/DOR CTRL
DF/DOR CTRL Function
0 0 DAC Register Contents Overridden by All 0s
0 1 DAC Register Contents Overridden by All 1s
1 0 Left-Justified Input Data Selected
1 1 Right-Justified Input Data Selected
